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Merge pull request #1952 from nuntipat/fix-csr-def-cv32e41p 

Fix CSR register definition for the CV32E41P core
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enjoy-digital 2024-05-14 12:08:42 +02:00 committed by GitHub
parent 2613ae606a b0acf6136e
commit 9b6e231a1a
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2 changed files with 6 additions and 8 deletions
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4
litex/soc/cores/cpu/cv32e41p/crt0.S
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@ -116,10 +116,8 @@ bss_loop:
add a0,a0,4 add a0,a0,4
j bss_loop j bss_loop
bss_done: bss_done:
li a0, 0xFFFF0880 //FFFF0880 enable timer + external interrupt + fast interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
li a0, 0x7FFF0880 //7FFF0880 enable timer + external interrupt + fast interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
csrw mie,a0 csrw mie,a0
j main j main
infinit_loop: infinit_loop:
j infinit_loop j infinit_loop

10
litex/soc/cores/cpu/cv32e41p/csr-defs.h
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@ -4,8 +4,8 @@
#define CSR_MSTATUS_MIE 0x8 #define CSR_MSTATUS_MIE 0x8
#define CSR_IRQ_MASK 0x344 #define CSR_IRQ_MASK 0x304
#define CSR_IRQ_PENDING 0x304 #define CSR_IRQ_PENDING 0x344
#define FIRQ_OFFSET 16 #define FIRQ_OFFSET 16
#define CSR_DCACHE_INFO 0xCC0 #define CSR_DCACHE_INFO 0xCC0
@ -13,7 +13,7 @@
/* /*
For CV32E41P from https://docs.openhwgroup.org/projects/openhw-group-cv32e41p/control_status_registers.html For CV32E41P from https://docs.openhwgroup.org/projects/cv32e41p-user-manual/control_status_registers.html
Machine Interrupt Pending Register (mip): CSR_IRQ_MASK: 0x344 Machine Interrupt Pending Register (mip): CSR_IRQ_PENDING: 0x344
Machine Interrupt Enable Register (mie): CSR_IRQ_PENDING: 0x304 Machine Interrupt Enable Register (mie): CSR_IRQ_MASK: 0x304
*/ */