soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
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854e7cc908
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@ -811,12 +811,12 @@ class SoC(Module):
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# SoC CSR Interconnect ---------------------------------------------------------------------
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self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
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address_map = self.csr.address_map,
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data_width = self.csr.data_width,
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address_width = self.csr.address_width,
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alignment = self.csr.alignment,
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paging = self.csr.paging,
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)
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address_map = self.csr.address_map,
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data_width = self.csr.data_width,
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address_width = self.csr.address_width,
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alignment = self.csr.alignment,
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paging = self.csr.paging,
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soc_bus_data_width = self.bus.data_width)
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if len(self.csr.masters):
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self.submodules.csr_interconnect = csr_bus.InterconnectShared(
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masters = list(self.csr.masters.values()),
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@ -78,11 +78,11 @@ class InterconnectShared(Module):
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class SRAM(Module):
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def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None, paging=0x800):
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def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None, paging=0x800, soc_bus_data_width=32):
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if bus is None:
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bus = Interface()
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self.bus = bus
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aligned_paging = paging//(bus.alignment//8)
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aligned_paging = paging//(soc_bus_data_width//8)
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data_width = len(self.bus.dat_w)
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if isinstance(mem_or_size, Memory):
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mem = mem_or_size
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@ -91,7 +91,7 @@ class SRAM(Module):
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mem_size = int(mem.width*mem.depth/8)
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if mem_size > aligned_paging:
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print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format(
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paging//4, mem_size))
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aligned_paging, mem_size))
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csrw_per_memw = (mem.width + data_width - 1)//data_width
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word_bits = log2_int(csrw_per_memw)
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page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
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@ -105,7 +105,7 @@ class SRAM(Module):
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else:
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read_only = False
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###
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# # #
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port = mem.get_port(write_capable=not read_only)
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self.specials += mem, port
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@ -162,12 +162,13 @@ class SRAM(Module):
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class CSRBank(csr.GenericBank):
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def __init__(self, description, address=0, bus=None, paging=0x800):
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def __init__(self, description, address=0, bus=None, paging=0x800, soc_bus_data_width=32):
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if bus is None:
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bus = Interface()
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self.bus = bus
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aligned_paging = paging//(bus.alignment//8)
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###
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aligned_paging = paging//(soc_bus_data_width//8)
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# # #
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csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
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@ -176,7 +177,7 @@ class CSRBank(csr.GenericBank):
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if bus.alignment == 64:
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self.comb += If(self.bus.adr[0], sel.eq(0))
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adr_shift = log2_int(bus.alignment//32)
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adr_shift = log2_int(bus.alignment//soc_bus_data_width)
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for i, c in enumerate(self.simple_csrs):
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self.comb += [
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@ -203,10 +204,11 @@ class CSRBank(csr.GenericBank):
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# address_map is called exactly once for each object at each call to
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# scan(), so it can have side effects.
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class CSRBankArray(Module):
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def __init__(self, source, address_map, *ifargs, paging=0x800, **ifkwargs):
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self.source = source
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self.address_map = address_map
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self.paging = paging
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def __init__(self, source, address_map, *ifargs, paging=0x800, soc_bus_data_width=32, **ifkwargs):
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self.source = source
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self.address_map = address_map
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self.paging = paging
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self.soc_bus_data_width = soc_bus_data_width
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self.scan(ifargs, ifkwargs)
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def scan(self, ifargs, ifkwargs):
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@ -229,8 +231,10 @@ class CSRBankArray(Module):
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if mapaddr is None:
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continue
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sram_bus = Interface(*ifargs, **ifkwargs)
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mmap = SRAM(memory, mapaddr, read_only=read_only,
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bus=sram_bus, paging=self.paging)
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mmap = SRAM(memory, mapaddr,
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read_only = read_only,
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bus = sram_bus,
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paging = self.paging)
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self.submodules += mmap
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csrs += mmap.get_csrs()
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self.srams.append((name, memory, mapaddr, mmap))
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@ -242,7 +246,10 @@ class CSRBankArray(Module):
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if mapaddr is None:
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continue
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bank_bus = Interface(*ifargs, **ifkwargs)
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rmap = CSRBank(csrs, mapaddr, bus=bank_bus, paging=self.paging)
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rmap = CSRBank(csrs, mapaddr,
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bus = bank_bus,
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paging = self.paging,
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soc_bus_data_width = self.soc_bus_data_width)
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self.submodules += rmap
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self.banks.append((name, csrs, mapaddr, rmap))
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