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soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)

This commit is contained in:
Florent Kermarrec 2020-02-18 09:11:40 +01:00
parent 854e7cc908
commit 9baa3ad5bb
2 changed files with 28 additions and 21 deletions
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2
litex/soc/integration/soc.py
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@ -816,7 +816,7 @@ class SoC(Module):
address_width = self.csr.address_width, address_width = self.csr.address_width,
alignment = self.csr.alignment, alignment = self.csr.alignment,
paging = self.csr.paging, paging = self.csr.paging,
) soc_bus_data_width = self.bus.data_width)
if len(self.csr.masters): if len(self.csr.masters):
self.submodules.csr_interconnect = csr_bus.InterconnectShared( self.submodules.csr_interconnect = csr_bus.InterconnectShared(
masters = list(self.csr.masters.values()), masters = list(self.csr.masters.values()),

27
litex/soc/interconnect/csr_bus.py
View File

@ -78,11 +78,11 @@ class InterconnectShared(Module):
class SRAM(Module): class SRAM(Module):
def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None, paging=0x800): def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None, paging=0x800, soc_bus_data_width=32):
if bus is None: if bus is None:
bus = Interface() bus = Interface()
self.bus = bus self.bus = bus
aligned_paging = paging//(bus.alignment//8) aligned_paging = paging//(soc_bus_data_width//8)
data_width = len(self.bus.dat_w) data_width = len(self.bus.dat_w)
if isinstance(mem_or_size, Memory): if isinstance(mem_or_size, Memory):
mem = mem_or_size mem = mem_or_size
@ -91,7 +91,7 @@ class SRAM(Module):
mem_size = int(mem.width*mem.depth/8) mem_size = int(mem.width*mem.depth/8)
if mem_size > aligned_paging: if mem_size > aligned_paging:
print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format( print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format(
paging//4, mem_size)) aligned_paging, mem_size))
csrw_per_memw = (mem.width + data_width - 1)//data_width csrw_per_memw = (mem.width + data_width - 1)//data_width
word_bits = log2_int(csrw_per_memw) word_bits = log2_int(csrw_per_memw)
page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False) page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
@ -162,11 +162,12 @@ class SRAM(Module):
class CSRBank(csr.GenericBank): class CSRBank(csr.GenericBank):
def __init__(self, description, address=0, bus=None, paging=0x800): def __init__(self, description, address=0, bus=None, paging=0x800, soc_bus_data_width=32):
if bus is None: if bus is None:
bus = Interface() bus = Interface()
self.bus = bus self.bus = bus
aligned_paging = paging//(bus.alignment//8) aligned_paging = paging//(soc_bus_data_width//8)
# # # # # #
csr.GenericBank.__init__(self, description, len(self.bus.dat_w)) csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
@ -176,7 +177,7 @@ class CSRBank(csr.GenericBank):
if bus.alignment == 64: if bus.alignment == 64:
self.comb += If(self.bus.adr[0], sel.eq(0)) self.comb += If(self.bus.adr[0], sel.eq(0))
adr_shift = log2_int(bus.alignment//32) adr_shift = log2_int(bus.alignment//soc_bus_data_width)
for i, c in enumerate(self.simple_csrs): for i, c in enumerate(self.simple_csrs):
self.comb += [ self.comb += [
@ -203,10 +204,11 @@ class CSRBank(csr.GenericBank):
# address_map is called exactly once for each object at each call to # address_map is called exactly once for each object at each call to
# scan(), so it can have side effects. # scan(), so it can have side effects.
class CSRBankArray(Module): class CSRBankArray(Module):
def __init__(self, source, address_map, *ifargs, paging=0x800, **ifkwargs): def __init__(self, source, address_map, *ifargs, paging=0x800, soc_bus_data_width=32, **ifkwargs):
self.source = source self.source = source
self.address_map = address_map self.address_map = address_map
self.paging = paging self.paging = paging
self.soc_bus_data_width = soc_bus_data_width
self.scan(ifargs, ifkwargs) self.scan(ifargs, ifkwargs)
def scan(self, ifargs, ifkwargs): def scan(self, ifargs, ifkwargs):
@ -229,8 +231,10 @@ class CSRBankArray(Module):
if mapaddr is None: if mapaddr is None:
continue continue
sram_bus = Interface(*ifargs, **ifkwargs) sram_bus = Interface(*ifargs, **ifkwargs)
mmap = SRAM(memory, mapaddr, read_only=read_only, mmap = SRAM(memory, mapaddr,
bus=sram_bus, paging=self.paging) read_only = read_only,
bus = sram_bus,
paging = self.paging)
self.submodules += mmap self.submodules += mmap
csrs += mmap.get_csrs() csrs += mmap.get_csrs()
self.srams.append((name, memory, mapaddr, mmap)) self.srams.append((name, memory, mapaddr, mmap))
@ -242,7 +246,10 @@ class CSRBankArray(Module):
if mapaddr is None: if mapaddr is None:
continue continue
bank_bus = Interface(*ifargs, **ifkwargs) bank_bus = Interface(*ifargs, **ifkwargs)
rmap = CSRBank(csrs, mapaddr, bus=bank_bus, paging=self.paging) rmap = CSRBank(csrs, mapaddr,
bus = bank_bus,
paging = self.paging,
soc_bus_data_width = self.soc_bus_data_width)
self.submodules += rmap self.submodules += rmap
self.banks.append((name, csrs, mapaddr, rmap)) self.banks.append((name, csrs, mapaddr, rmap))