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Merge pull request #1517 from shenki/nerov32 

test_cpu: Add NeoRV32 to tested CPUs
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enjoy-digital 2022-11-21 08:24:25 +01:00 committed by GitHub
parent 6b4696e3e0 b30dd0b5c6
commit 9bb1a261dc
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test/test_cpu.py
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@ -42,6 +42,7 @@ class TestCPU(unittest.TestCase):
"firev", # (riscv / softcore) "firev", # (riscv / softcore)
"marocchino", # (or1k / softcore) "marocchino", # (or1k / softcore)
"naxriscv", # (riscv / softcore) "naxriscv", # (riscv / softcore)
"neorv32", # (riscv / softcore)
"serv", # (riscv / softcore) "serv", # (riscv / softcore)
"vexriscv", # (riscv / softcore) "vexriscv", # (riscv / softcore)
"vexriscv_smp", # (riscv / softcore) "vexriscv_smp", # (riscv / softcore)
@ -60,7 +61,6 @@ class TestCPU(unittest.TestCase):
"lm32", # (lm32 / softcore) -> Requires LM32 toolchain. "lm32", # (lm32 / softcore) -> Requires LM32 toolchain.
"minerva", # (riscv / softcore) -> Broken install? (Amaranth?) "minerva", # (riscv / softcore) -> Broken install? (Amaranth?)
"mor1kx", # (or1k / softcore) -> Verilator compilation issue. "mor1kx", # (or1k / softcore) -> Verilator compilation issue.
"neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys).
"picorv32", # (riscv / softcore) -> Verilator compilation issue. "picorv32", # (riscv / softcore) -> Verilator compilation issue.
"rocket", # (riscv / softcore) -> Not enough RAM in CI. "rocket", # (riscv / softcore) -> Not enough RAM in CI.
"zynq7000", # (arm / hardcore) -> Hardcore. "zynq7000", # (arm / hardcore) -> Hardcore.