soc/integration/soc.py: Fix creation of AHB2Wishbone bridge

Don't do bus_addressing_convert as it's being handled in AHB2Wishbone
logic.

Add addressing parameters for AHBInterface constructor as required
by soc code.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang 2024-06-17 13:34:20 +01:00
parent 22f9c063db
commit 9bdc22adfb
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2 changed files with 8 additions and 4 deletions

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@ -30,6 +30,7 @@ from litex.soc.interconnect import csr_bus
from litex.soc.interconnect import stream from litex.soc.interconnect import stream
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.interconnect import axi from litex.soc.interconnect import axi
from litex.soc.interconnect import ahb
# Helpers ------------------------------------------------------------------------------------------ # Helpers ------------------------------------------------------------------------------------------
@ -364,8 +365,8 @@ class SoCBusHandler(LiteXModule):
# Same Addressing, return un-modified interface. # Same Addressing, return un-modified interface.
if interface.addressing == self.addressing: if interface.addressing == self.addressing:
return interface return interface
# AXI/AXI-Lite interface, Bus-Addressing conversion already handled in Bus-Standard conversion. # AXI/AXI-Lite/AHB interface, Bus-Addressing conversion already handled in Bus-Standard conversion.
elif isinstance(interface, (axi.AXIInterface, axi.AXILiteInterface)): elif isinstance(interface, (axi.AXIInterface, axi.AXILiteInterface, ahb.AHBInterface)):
return interface return interface
# Different Addressing: Return adapted interface. # Different Addressing: Return adapted interface.
else: else:
@ -419,6 +420,7 @@ class SoCBusHandler(LiteXModule):
(axi.AXILiteInterface, axi.AXIInterface) : axi.AXILite2AXI, (axi.AXILiteInterface, axi.AXIInterface) : axi.AXILite2AXI,
(axi.AXIInterface, axi.AXILiteInterface): axi.AXI2AXILite, (axi.AXIInterface, axi.AXILiteInterface): axi.AXI2AXILite,
(axi.AXIInterface, wishbone.Interface) : axi.AXI2Wishbone, (axi.AXIInterface, wishbone.Interface) : axi.AXI2Wishbone,
(ahb.AHBInterface, wishbone.Interface) : ahb.AHB2Wishbone,
}[type(master), type(slave)] }[type(master), type(slave)]
bridge = bridge_cls(master, slave) bridge = bridge_cls(master, slave)
self.submodules += bridge self.submodules += bridge
@ -436,6 +438,7 @@ class SoCBusHandler(LiteXModule):
wishbone.Interface: "Wishbone", wishbone.Interface: "Wishbone",
axi.AXILiteInterface: "AXI-Lite", axi.AXILiteInterface: "AXI-Lite",
axi.AXIInterface: "AXI", axi.AXIInterface: "AXI",
ahb.AHBInterface: "AHB",
} }
self.logger.info(fmt.format( self.logger.info(fmt.format(
name = colorer(name), name = colorer(name),

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@ -41,11 +41,12 @@ def ahb_description(data_width, address_width):
] ]
class AHBInterface(Record): class AHBInterface(Record):
def __init__(self, data_width=32, address_width=32): def __init__(self, data_width=32, address_width=32, addressing="byte"):
assert addressing == "byte"
Record.__init__(self, ahb_description(data_width, address_width)) Record.__init__(self, ahb_description(data_width, address_width))
self.data_width = data_width self.data_width = data_width
self.address_width = address_width self.address_width = address_width
self.addressing = "byte" self.addressing = addressing
# AHB to Wishbone --------------------------------------------------------------------------------- # AHB to Wishbone ---------------------------------------------------------------------------------