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soc/add_ethernet: Add with_timestamp parameter to enable Timestamping and use timer0.uptime_cycles as Timestamp source.

This commit is contained in:
Florent Kermarrec 2021-04-08 14:37:03 +02:00
parent 7caed56790
commit 9bec0ce7a2
1 changed files with 7 additions and 1 deletions
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8
litex/soc/integration/soc.py
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@ -1365,13 +1365,18 @@ class LiteXSoC(SoC):
base_address = self.bus.regions["main_ram"].origin) base_address = self.bus.regions["main_ram"].origin)
# Add Ethernet --------------------------------------------------------------------------------- # Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False, nrxslots=2, ntxslots=2): def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False,
nrxslots = 2,
ntxslots = 2,
with_timestamp = False):
# Imports # Imports
from liteeth.mac import LiteEthMAC from liteeth.mac import LiteEthMAC
from liteeth.phy.model import LiteEthPHYModel from liteeth.phy.model import LiteEthPHYModel
# MAC. # MAC.
self.check_if_exists(name) self.check_if_exists(name)
if with_timestamp:
self.timer0.add_uptime()
ethmac = LiteEthMAC( ethmac = LiteEthMAC(
phy = phy, phy = phy,
dw = 32, dw = 32,
@ -1379,6 +1384,7 @@ class LiteXSoC(SoC):
endianness = self.cpu.endianness, endianness = self.cpu.endianness,
nrxslots = nrxslots, nrxslots = nrxslots,
ntxslots = ntxslots, ntxslots = ntxslots,
timestamp = None if not with_timestamp else self.timer0.uptime_cycles,
with_preamble_crc = not software_debug) with_preamble_crc = not software_debug)
# Use PHY's eth_tx/eth_rx clock domains. # Use PHY's eth_tx/eth_rx clock domains.
ethmac = ClockDomainsRenamer({ ethmac = ClockDomainsRenamer({