test/test_cpu: Re-enable cv32e40p/marocchino.
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@ -36,13 +36,12 @@ class TestCPU(unittest.TestCase):
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def test_cpu(self):
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tested_cpus = [
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#"cv32e40p", # (riscv / softcore)
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"cv32e40p", # (riscv / softcore)
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"femtorv", # (riscv / softcore)
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"firev", # (riscv / softcore)
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"ibex", # (riscv / softcore)
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#"marocchino", # (or1k / softcore)
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"marocchino", # (or1k / softcore)
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"naxriscv", # (riscv / softcore)
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#"rocket", # (riscv / softcore)
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"serv", # (riscv / softcore)
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"vexriscv", # (riscv / softcore)
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"vexriscv_smp", # (riscv / softcore)
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@ -62,6 +61,7 @@ class TestCPU(unittest.TestCase):
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"mor1kx", # (or1k / softcore) -> Verilator compilation issue.
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"neorv32", # (riscv / softcore) -> Requires VHDL->Verilog (GHDL + Yosys).
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"picorv32", # (riscv / softcore) -> Verilator compilation issue.
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"rocket", # (riscv / softcore) -> Not enough RAM in CI.
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"zynq7000", # (arm / hardcore) -> Hardcore.
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"zynqmp", # (aarch64 / hardcore) -> Hardcore.
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]
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