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cpu/naxriscv: Add --no-netlist-cache
Ignores the netlist cache. When you hack on naxriscv code, you always want fresh results.
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1 changed files with 3 additions and 1 deletions
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@ -99,6 +99,7 @@ class NaxRiscv(CPU):
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cpu_group.add_argument("--with-jtag-tap", action="store_true", help="Add a embedded JTAG tap for debugging")
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cpu_group.add_argument("--with-jtag-instruction", action="store_true", help="Add a JTAG instruction port which implement tunneling for debugging (TAP not included)")
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cpu_group.add_argument("--update-repo", default="recommended", choices=["latest","wipe+latest","recommended","wipe+recommended","no"], help="Specify how the NaxRiscv & SpinalHDL repo should be updated (latest: update to HEAD, recommended: Update to known compatible version, no: Don't update, wipe+*: Do clean&reset before checkout)")
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cpu_group.add_argument("--no-netlist-cache", action="store_true", help="Always (re-)build the netlist")
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@staticmethod
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def args_read(args):
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@ -106,6 +107,7 @@ class NaxRiscv(CPU):
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NaxRiscv.jtag_tap = args.with_jtag_tap
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NaxRiscv.jtag_instruction = args.with_jtag_instruction
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NaxRiscv.update_repo = args.update_repo
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NaxRiscv.no_netlist_cache = args.no_netlist_cache
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if args.scala_file:
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NaxRiscv.scala_files = args.scala_file
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if args.scala_args:
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@ -265,7 +267,7 @@ class NaxRiscv(CPU):
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def add_sources(self, platform):
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vdir = get_data_mod("cpu", "naxriscv").data_location
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print(f"NaxRiscv netlist : {self.netlist_name}")
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if not os.path.exists(os.path.join(vdir, self.netlist_name + ".v")):
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if NaxRiscv.no_netlist_cache or not os.path.exists(os.path.join(vdir, self.netlist_name + ".v")):
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self.generate_netlist(self.reset_address)
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# Add RAM.
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