fhdl: RenameClockDomains decorator

migen/fhdl/decorators.py

@@ -1,5 +1,5 @@
 from migen.fhdl.structure import *
-from migen.fhdl.tools import insert_reset
+from migen.fhdl.tools import insert_reset, rename_clock_domain
 
 class ModuleDecorator:
 	def __init__(self, decorated):
@@ -78,3 +78,14 @@ class InsertReset(InsertControl):
 	def transform_fragment_insert(self, f, to_insert):
 		for reset, cdn in to_insert:
 			f.sync[cdn] = insert_reset(reset, f.sync[cdn])
+
+class RenameClockDomains(ModuleDecorator):
+	def __init__(self, decorated, cd_remapping):
+		ModuleDecorator.__init__(self, decorated)
+		if isinstance(cd_remapping, str):
+			cd_remapping = {"sys": cd_remapping}
+		object.__setattr__(self, "_rc_cd_remapping", cd_remapping)
+
+	def transform_fragment(self, f):
+		for old, new in self._rc_cd_remapping.items():
+			rename_clock_domain(f, old, new)

migen/fhdl/module.py

@@ -68,11 +68,11 @@ class _ModuleSpecials(_ModuleProxy, _ModuleForwardAttr):
 
 class _ModuleSubmodules(_ModuleProxy):
 	def __setattr__(self, name, value):
-		self._fm._submodules += [(name, e, dict()) for e in _flat_list(value)]
+		self._fm._submodules += [(name, e) for e in _flat_list(value)]
 		setattr(self._fm, name, value)
 	
 	def __iadd__(self, other):
-		self._fm._submodules += [(None, e, dict()) for e in _flat_list(other)]
+		self._fm._submodules += [(None, e) for e in _flat_list(other)]
 		return self
 
 class _ModuleClockDomains(_ModuleProxy, _ModuleForwardAttr):
@@ -131,20 +131,8 @@ class Module:
 		else:
 			object.__setattr__(self, name, value)
 
-	def add_submodule(self, submodule, cd_remapping=dict(), name=None):
-		if isinstance(cd_remapping, str):
-			cd_remapping = {"sys": cd_remapping}
-		if name is not None:
-			setattr(self, name, submodule)
-		self._submodules.append((name, submodule, cd_remapping))
-
 	def _collect_submodules(self):
-		r = []
-		for name, submodule, cd_remapping in self._submodules:
-			f = submodule.get_fragment()
-			for old, new in cd_remapping.items():
-				rename_clock_domain(f, old, new)
-			r.append((name, f))
+		r = [(name, submodule.get_fragment()) for name, submodule in self._submodules]
 		self._submodules = []
 		return r
 

migen/fhdl/std.py

@@ -2,4 +2,4 @@ from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import TSTriple, Instance, Memory
 from migen.fhdl.size import log2_int, bits_for, flen
-from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset
+from migen.fhdl.decorators import DecorateModule, InsertCE, InsertReset, RenameClockDomains

migen/genlib/fifo.py

@@ -88,10 +88,9 @@ class AsyncFIFO(Module, _FIFOInterface):
 
 		depth_bits = log2_int(depth, True)
 
-		produce = GrayCounter(depth_bits+1)
-		self.add_submodule(produce, "write")
-		consume = GrayCounter(depth_bits+1)
-		self.add_submodule(consume, "read")
+		produce = RenameClockDomains(GrayCounter(depth_bits+1), "write")
+		consume = RenameClockDomains(GrayCounter(depth_bits+1), "read")
+		self.submodules += produce, consume
 		self.comb += [
 			produce.ce.eq(self.writable & self.we),
 			consume.ce.eq(self.readable & self.re)