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soc_zynq: move axi gp0 clock connection to add_gp0 method

This commit is contained in:
Florent Kermarrec 2019-07-10 16:50:06 +02:00
parent b0192e5f8b
commit 9c8c037108
1 changed files with 3 additions and 3 deletions
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6
litex/soc/integration/soc_zynq.py
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@ -72,9 +72,6 @@ class SoCZynq(SoCCore):
# fabric clk # fabric clk
o_FCLK_CLK0=ClockSignal("sys"), o_FCLK_CLK0=ClockSignal("sys"),
# axi gp0 clk
i_M_AXI_GP0_ACLK=ClockSignal("sys"),
) )
platform.add_ip(os.path.join("ip", ps7_name + ".xci")) platform.add_ip(os.path.join("ip", ps7_name + ".xci"))
@ -83,6 +80,9 @@ class SoCZynq(SoCCore):
def add_gp0(self): def add_gp0(self):
self.axi_gp0 = axi_gp0 = axi.AXIInterface(data_width=32, address_width=32, id_width=12) self.axi_gp0 = axi_gp0 = axi.AXIInterface(data_width=32, address_width=32, id_width=12)
self.ps7_params.update( self.ps7_params.update(
# axi gp0 clk
i_M_AXI_GP0_ACLK=ClockSignal("sys"),
# axi gp0 aw # axi gp0 aw
o_M_AXI_GP0_AWVALID=axi_gp0.aw.valid, o_M_AXI_GP0_AWVALID=axi_gp0.aw.valid,
i_M_AXI_GP0_AWREADY=axi_gp0.aw.ready, i_M_AXI_GP0_AWREADY=axi_gp0.aw.ready,