interconnect/stream: Switch to LiteXModule.
This commit is contained in:
Florent Kermarrec
parent
002aad7a43
commit
9ccac7f7e0
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@ -13,7 +13,7 @@ from migen.util.misc import xdir
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from migen.genlib import fifo
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from migen.genlib.cdc import MultiReg, PulseSynchronizer, AsyncResetSynchronizer
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from litex.gen import LiteXContext
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from litex.gen import *
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from litex.soc.interconnect.csr import *
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@ -108,7 +108,7 @@ def get_single_ep(obj, filt):
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return list(eps.items())[0]
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class BinaryActor(Module):
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class BinaryActor(LiteXModule):
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def __init__(self, *args, **kwargs):
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self.build_binary_control(self.sink, self.source, *args, **kwargs)
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@ -167,7 +167,7 @@ class PipelinedActor(BinaryActor):
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# FIFO ---------------------------------------------------------------------------------------------
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class _FIFOWrapper(Module):
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class _FIFOWrapper(LiteXModule):
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def __init__(self, fifo_class, layout, depth):
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self.sink = sink = Endpoint(layout)
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self.source = source = Endpoint(layout)
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@ -182,7 +182,7 @@ class _FIFOWrapper(Module):
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("last", 1)
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]
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self.submodules.fifo = fifo = fifo_class(layout_len(fifo_layout), depth)
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self.fifo = fifo = fifo_class(layout_len(fifo_layout), depth)
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fifo_in = Record(fifo_layout)
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fifo_out = Record(fifo_layout)
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self.comb += [
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@ -244,7 +244,7 @@ class AsyncFIFO(_FIFOWrapper):
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# ClockDomainCrossing ------------------------------------------------------------------------------
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class ClockDomainCrossing(Module):
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class ClockDomainCrossing(LiteXModule):
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def __init__(self, layout, cd_from="sys", cd_to="sys", depth=None, buffered=False, with_common_rst=False):
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self.sink = Endpoint(layout)
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self.source = Endpoint(layout)
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@ -288,7 +288,7 @@ class ClockDomainCrossing(Module):
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# Mux/Demux ----------------------------------------------------------------------------------------
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class Multiplexer(Module):
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class Multiplexer(LiteXModule):
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def __init__(self, layout, n):
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self.source = Endpoint(layout)
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sinks = []
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@ -306,7 +306,7 @@ class Multiplexer(Module):
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self.comb += Case(self.sel, cases)
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class Demultiplexer(Module):
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class Demultiplexer(LiteXModule):
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def __init__(self, layout, n):
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self.sink = Endpoint(layout)
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sources = []
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@ -326,7 +326,7 @@ class Demultiplexer(Module):
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# Gate ---------------------------------------------------------------------------------------------
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class Gate(Module):
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class Gate(LiteXModule):
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def __init__(self, layout, sink_ready_when_disabled=False):
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self.sink = Endpoint(layout)
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self.source = Endpoint(layout)
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@ -344,7 +344,7 @@ class Gate(Module):
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# Converter ----------------------------------------------------------------------------------------
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class _UpConverter(Module):
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class _UpConverter(LiteXModule):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to), ("valid_token_count", bits_for(ratio))])
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@ -399,7 +399,7 @@ class _UpConverter(Module):
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self.sync += If(load_part, source.valid_token_count.eq(demux + 1))
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class _DownConverter(Module):
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class _DownConverter(LiteXModule):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to), ("valid_token_count", 1)])
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@ -439,7 +439,7 @@ class _DownConverter(Module):
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self.comb += source.valid_token_count.eq(last)
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class _IdentityConverter(Module):
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class _IdentityConverter(LiteXModule):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to), ("valid_token_count", 1)])
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@ -470,7 +470,7 @@ def _get_converter_ratio(nbits_from, nbits_to):
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return converter_cls, ratio
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class Converter(Module):
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class Converter(LiteXModule):
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def __init__(self, nbits_from, nbits_to,
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reverse = False,
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report_valid_token_count = False):
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@ -490,7 +490,7 @@ class Converter(Module):
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self.comb += converter.source.connect(self.source, omit=set(["valid_token_count"]))
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class StrideConverter(Module):
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class StrideConverter(LiteXModule):
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def __init__(self, description_from, description_to, reverse=False):
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self.sink = sink = Endpoint(description_from)
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self.source = source = Endpoint(description_to)
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@ -560,7 +560,7 @@ def inc_mod(s, m):
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return [s.eq(s + 1), If(s == (m -1), s.eq(0))]
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class Gearbox(Module):
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class Gearbox(LiteXModule):
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def __init__(self, i_dw, o_dw, msb_first=True):
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self.sink = sink = Endpoint([("data", i_dw)])
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self.source = source = Endpoint([("data", o_dw)])
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@ -647,7 +647,7 @@ class Shifter(PipelinedActor):
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# Monitor ------------------------------------------------------------------------------------------
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class Monitor(Module, AutoCSR):
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class Monitor(LiteXModule):
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def __init__(self, endpoint, count_width=32, clock_domain="sys",
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with_tokens = False,
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with_overflows = False,
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@ -707,7 +707,7 @@ class Monitor(Module, AutoCSR):
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# Tokens Count -----------------------------------------------------------------------------
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if with_tokens:
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self.submodules.token_counter = MonitorCounter(
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self.token_counter = MonitorCounter(
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reset = reset,
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latch = latch,
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enable = endpoint.valid & endpoint.ready,
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@ -716,7 +716,7 @@ class Monitor(Module, AutoCSR):
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# Overflows Count (only useful when endpoint is expected to always be ready) ---------------
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if with_overflows:
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self.submodules.overflow_counter = MonitorCounter(
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self.overflow_counter = MonitorCounter(
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reset = reset,
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latch = latch,
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enable = endpoint.valid & ~endpoint.ready,
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@ -725,7 +725,7 @@ class Monitor(Module, AutoCSR):
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# Underflows Count (only useful when endpoint is expected to always be valid) --------------
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if with_underflows:
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self.submodules.underflow_counter = MonitorCounter(
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self.underflow_counter = MonitorCounter(
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reset = reset,
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latch = latch,
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enable = ~endpoint.valid & endpoint.ready,
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@ -734,7 +734,7 @@ class Monitor(Module, AutoCSR):
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# Packets Count ----------------------------------------------------------------------------
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if with_packets:
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self.submodules.packet_counter = MonitorCounter(
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self.packet_counter = MonitorCounter(
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reset = reset,
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latch = latch,
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enable = endpoint.valid & getattr(endpoint, packet_delimiter) & endpoint.ready,
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@ -743,7 +743,7 @@ class Monitor(Module, AutoCSR):
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# Pipe ---------------------------------------------------------------------------------------------
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class PipeValid(Module):
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class PipeValid(LiteXModule):
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"""Pipe valid/payload to cut timing path"""
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def __init__(self, layout):
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self.sink = sink = Endpoint(layout)
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@ -764,7 +764,7 @@ class PipeValid(Module):
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self.comb += sink.ready.eq(~source.valid | source.ready)
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class PipeReady(Module):
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class PipeReady(LiteXModule):
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"""Pipe ready to cut timing path"""
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def __init__(self, layout):
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self.sink = sink = Endpoint(layout)
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@ -796,7 +796,7 @@ class PipeReady(Module):
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# Buffer -------------------------------------------------------------------------------------------
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class Buffer(Module):
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class Buffer(LiteXModule):
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"""Pipe valid/payload and/or ready to cut timing path"""
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def __init__(self, layout, pipe_valid=True, pipe_ready=False):
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self.sink = sink = Endpoint(layout)
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@ -808,16 +808,16 @@ class Buffer(Module):
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# Pipe Valid (Optional).
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if pipe_valid:
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self.submodules.pipe_valid = PipeValid(layout)
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self.pipe_valid = PipeValid(layout)
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pipeline.append(self.pipe_valid)
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# Pipe Ready (Optional).
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if pipe_ready:
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self.submodules.pipe_ready = PipeReady(layout)
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self.pipe_ready = PipeReady(layout)
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pipeline.append(self.pipe_ready)
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# Buffer Pipeline.
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self.submodules.pipeline = Pipeline(
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self.pipeline = Pipeline(
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sink,
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*pipeline,
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source
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@ -845,7 +845,7 @@ class Cast(CombinatorialActor):
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# Unpack/Pack --------------------------------------------------------------------------------------
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class Unpack(Module):
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class Unpack(LiteXModule):
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def __init__(self, n, layout_to, reverse=False):
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self.source = source = Endpoint(layout_to)
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description_from = Endpoint(layout_to).description
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@ -889,7 +889,7 @@ class Unpack(Module):
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]
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class Pack(Module):
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class Pack(LiteXModule):
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def __init__(self, layout_from, n, reverse=False):
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self.sink = sink = Endpoint(layout_from)
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description_to = Endpoint(layout_from).description
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@ -941,7 +941,7 @@ class Pack(Module):
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# Pipeline -----------------------------------------------------------------------------------------
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class Pipeline(Module):
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class Pipeline(LiteXModule):
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def __init__(self, *modules):
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self.modules = list(modules)
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if len(self.modules):
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