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cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that.

This commit is contained in:
Florent Kermarrec 2020-05-13 09:31:20 +02:00
parent 5ea3bae036
commit 9d1443c1a8
2 changed files with 2 additions and 2 deletions
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1
litex/soc/cores/cpu/__init__.py
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@ -28,6 +28,7 @@ class CPUNone(CPU):
io_regions = {0x00000000: 0x100000000} # origin, length io_regions = {0x00000000: 0x100000000} # origin, length
periph_buses = [] periph_buses = []
memory_buses = [] memory_buses = []
mem_map = {"csr": 0x00000000}
CPU_GCC_TRIPLE_RISCV32 = ( CPU_GCC_TRIPLE_RISCV32 = (
"riscv64-unknown-elf", "riscv64-unknown-elf",

3
litex/soc/integration/soc_core.py
View File

@ -85,7 +85,6 @@ class SoCCore(LiteXSoC):
csr_alignment = 32, csr_alignment = 32,
csr_address_width = 14, csr_address_width = 14,
csr_paging = 0x800, csr_paging = 0x800,
csr_base = None,
# Identifier parameters # Identifier parameters
ident = "", ident = "",
ident_version = False, ident_version = False,
@ -185,7 +184,7 @@ class SoCCore(LiteXSoC):
self.add_timer(name="timer0") self.add_timer(name="timer0")
# Add CSR bridge # Add CSR bridge
self.add_csr_bridge(self.mem_map["csr"] if csr_base is None else csr_base) self.add_csr_bridge(self.mem_map["csr"])
# Methods -------------------------------------------------------------------------------------- # Methods --------------------------------------------------------------------------------------