Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

coding.py: rewrite If() to make verilog more readable

Browse source
This commit is contained in:
Robert Jördens 2013-06-29 21:25:06 -06:00 committed by Sebastien Bourdeauducq
parent b0d467d744
commit 9d241f8cd3
1 changed files with 2 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
migen/genlib/coding.py
View file

@ -22,10 +22,8 @@ class PriorityEncoder(Module):
self.i = Signal(width) # one-hot, lsb has priority self.i = Signal(width) # one-hot, lsb has priority
self.o = Signal(max=width) # binary self.o = Signal(max=width) # binary
self.n = Signal() # none self.n = Signal() # none
act = If(0) for j in range(width)[::-1]: # last has priority
for j in range(width): self.comb += If(self.i[j], self.o.eq(j))
act = act.Elif(self.i[j], self.o.eq(j))
self.comb += act
self.comb += self.n.eq(self.i == 0) self.comb += self.n.eq(self.i == 0)
class Decoder(Module): class Decoder(Module):
@ -41,9 +39,7 @@ class PriorityDecoder(Decoder):
pass # same pass # same
def _main(): def _main():
from migen.sim.generic import Simulator, TopLevel
from migen.fhdl import verilog from migen.fhdl import verilog
e = Encoder(8) e = Encoder(8)
print(verilog.convert(e, ios={e.i, e.o, e.n})) print(verilog.convert(e, ios={e.i, e.o, e.n}))
pe = PriorityEncoder(8) pe = PriorityEncoder(8)