dvisampler: report FIFO overflow
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@ -1,5 +1,5 @@
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from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.record import Record
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from migen.bank.description import *
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@ -105,7 +105,7 @@ class ResolutionDetection(Module, AutoCSR):
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)
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self.specials += MultiReg(vcounter_st, self._vres.status)
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class FrameExtraction(Module):
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class FrameExtraction(Module, AutoCSR):
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def __init__(self):
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# in pix clock domain
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self.valid_i = Signal()
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@ -119,6 +119,8 @@ class FrameExtraction(Module):
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self.frame = Source(frame_layout)
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self.busy = Signal()
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self._r_overflow = CSR()
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###
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fifo_stb = Signal()
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@ -145,3 +147,36 @@ class FrameExtraction(Module):
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fifo.re.eq(self.frame.ack),
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self.busy.eq(0)
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]
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# overflow detection
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pix_overflow = Signal()
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pix_overflow_reset = Signal()
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self.sync.pix += [
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If(fifo.we & ~fifo.writable,
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pix_overflow.eq(1)
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).Elif(pix_overflow_reset,
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pix_overflow.eq(0)
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)
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]
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sys_overflow = Signal()
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self.specials += MultiReg(pix_overflow, sys_overflow)
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self.submodules.overflow_reset = PulseSynchronizer("sys", "pix")
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self.submodules.overflow_reset_ack = PulseSynchronizer("pix", "sys")
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self.comb += [
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pix_overflow_reset.eq(self.overflow_reset.o),
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self.overflow_reset_ack.i.eq(pix_overflow_reset)
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]
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overflow_mask = Signal()
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self.comb += [
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self._r_overflow.w.eq(sys_overflow & ~overflow_mask),
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self.overflow_reset.i.eq(self._r_overflow.re)
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]
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self.sync += [
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If(self._r_overflow.re,
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overflow_mask.eq(1)
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).Elif(self.overflow_reset_ack.o,
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overflow_mask.eq(0)
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)
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]
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@ -216,6 +216,14 @@ int dvisamplerX_phase_startup(void)
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}
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}
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static void dvisamplerX_check_overflow(void)
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{
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if(dvisamplerX_frame_overflow_read()) {
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printf("dvisamplerX: FIFO overflow\n");
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dvisamplerX_frame_overflow_write(1);
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}
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}
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static int dvisamplerX_locked;
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static int dvisamplerX_last_event;
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@ -239,4 +247,5 @@ void dvisamplerX_service(void)
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dvisamplerX_locked = 1;
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}
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}
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dvisamplerX_check_overflow();
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}
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