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sim: VCD generation
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parent
22b3c11b93
commit
9da512dbf5
2 changed files with 23 additions and 8 deletions
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@ -1,5 +1,5 @@
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from migen.fhdl.structure import *
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from migen.sim.generic import Simulator
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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class Counter:
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@ -21,7 +21,7 @@ class Counter:
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def main():
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dut = Counter()
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sim = Simulator(dut.get_fragment(), Runner())
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sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
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sim.run(10)
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main()
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@ -3,8 +3,11 @@ from migen.fhdl import verilog
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from migen.sim.ipc import *
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class TopLevel:
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def __init__(self, top_name="top", dut_type="dut", dut_name="dut", clk_name="sys_clk",
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clk_period=10, rst_name="sys_rst"):
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def __init__(self, vcd_name=None, vcd_level=1,
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top_name="top", dut_type="dut", dut_name="dut",
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clk_name="sys_clk", clk_period=10, rst_name="sys_rst"):
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self.vcd_name = vcd_name
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self.vcd_level = vcd_level
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self.top_name = top_name
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self.dut_type = dut_type
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self.dut_name = dut_name
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@ -13,7 +16,9 @@ class TopLevel:
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self.rst_name = rst_name
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def get(self, sockaddr):
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template = """module {top_name}();
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template1 = """`timescale 1ns / 1ps
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module {top_name}();
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reg {clk_name};
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reg {rst_name};
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@ -38,16 +43,26 @@ end
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initial $migensim_connect("{sockaddr}");
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always @(posedge {clk_name}) $migensim_tick;
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endmodule
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"""
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return template.format(top_name=self.top_name,
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template2 = """
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initial begin
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$dumpfile("{vcd_name}");
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$dumpvars({vcd_level}, {dut_name});
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end
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"""
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r = template1.format(top_name=self.top_name,
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dut_type=self.dut_type,
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dut_name=self.dut_name,
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clk_name=self.clk_name,
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hclk_period=str(self.clk_period/2),
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rst_name=self.rst_name,
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sockaddr=sockaddr)
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if self.vcd_name is not None:
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r += template2.format(vcd_name=self.vcd_name,
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vcd_level=str(self.vcd_level),
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dut_name=self.dut_name)
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r += "\nendmodule"
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return r
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class Simulator:
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def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket"):
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