add Icarus verilog simulation workaround (needed to simulate SATA core)
This commit is contained in:
Florent Kermarrec
parent
b70913b9a4
commit
9da8188b71
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@ -0,0 +1,131 @@
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From 7444442f068cff672071ba0d8a2008c7f53275e3 Mon Sep 17 00:00:00 2001
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From: Florent Kermarrec <florent@enjoy-digital.fr>
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Date: Fri, 23 Jan 2015 10:13:47 +0100
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Subject: [PATCH] workaround for icarus simulation (Copyright 2014 David
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Carne)
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---
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migen/fhdl/verilog.py | 51 +++++++++++++++++++++++++++++++++++----------------
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1 file changed, 35 insertions(+), 16 deletions(-)
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diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
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index b4bd534..c0ec678 100644
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--- a/migen/fhdl/verilog.py
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+++ b/migen/fhdl/verilog.py
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@@ -95,9 +95,13 @@ def _printexpr(ns, node):
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(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
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-def _printnode(ns, at, level, node):
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+def _printnode(ns, at, level, node, target_filter=None):
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if node is None:
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return ""
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+
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+ elif target_filter is not None and target_filter not in list_targets(node):
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+ return ""
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+
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elif isinstance(node, _Assign):
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if at == _AT_BLOCKING:
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assignment = " = "
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@@ -109,13 +113,13 @@ def _printnode(ns, at, level, node):
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assignment = " <= "
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return "\t"*level + _printexpr(ns, node.l)[0] + assignment + _printexpr(ns, node.r)[0] + ";\n"
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elif isinstance(node, (list, tuple)):
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- return "".join(list(map(partial(_printnode, ns, at, level), node)))
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+ return "".join(_printnode(ns, at, level, n, target_filter) for n in node)
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elif isinstance(node, If):
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r = "\t"*level + "if (" + _printexpr(ns, node.cond)[0] + ") begin\n"
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- r += _printnode(ns, at, level + 1, node.t)
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+ r += _printnode(ns, at, level + 1, node.t, target_filter)
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if node.f:
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r += "\t"*level + "end else begin\n"
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- r += _printnode(ns, at, level + 1, node.f)
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+ r += _printnode(ns, at, level + 1, node.f, target_filter)
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r += "\t"*level + "end\n"
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return r
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elif isinstance(node, Case):
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@@ -124,11 +128,12 @@ def _printnode(ns, at, level, node):
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css = sorted([(k, v) for (k, v) in node.cases.items() if k != "default"], key=itemgetter(0))
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for choice, statements in css:
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r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
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- r += _printnode(ns, at, level + 2, statements)
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+ r += _printnode(ns, at, level + 2, statements, target_filter)
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r += "\t"*(level + 1) + "end\n"
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if "default" in node.cases:
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r += "\t"*(level + 1) + "default: begin\n"
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- r += _printnode(ns, at, level + 2, node.cases["default"])
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+ r += _printnode(ns, at, level + 2, node.cases["default"],
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+ target_filter)
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r += "\t"*(level + 1) + "end\n"
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r += "\t"*level + "endcase\n"
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return r
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@@ -187,26 +192,40 @@ def _printcomb(f, ns, display_run):
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r += "reg " + _printsig(ns, dummy_s) + ";\n"
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r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
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r += syn_on
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+
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+ from collections import defaultdict
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+
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+ target_stmt_map = defaultdict(list)
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+
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+ for statement in flat_iteration(f.comb):
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+ targets = list_targets(statement)
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+ for t in targets:
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+ target_stmt_map[t].append(statement)
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+
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+ #from pprint import pprint
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+ #pprint(target_stmt_map)
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groups = group_by_targets(f.comb)
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+
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+ for n, (t, stmts) in enumerate(target_stmt_map.items()):
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+ assert isinstance(t, Signal)
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- for n, g in enumerate(groups):
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- if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
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- r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
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+ if len(stmts) == 1 and isinstance(stmts[0], _Assign):
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+ r += "assign " + _printnode(ns, _AT_BLOCKING, 0, stmts[0])
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else:
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dummy_d = Signal(name_override="dummy_d")
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r += "\n" + syn_off
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r += "reg " + _printsig(ns, dummy_d) + ";\n"
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r += syn_on
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-
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+
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r += "always @(*) begin\n"
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if display_run:
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r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
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- for t in g[0]:
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- r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
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- r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
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+
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+ r += "\t" + ns.get_name(t) + " = " + _printexpr(ns, t.reset)[0] + ";\n"
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+ r += _printnode(ns, _AT_BLOCKING, 1, stmts, t)
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r += syn_off
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- r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
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+ r += "\t" + ns.get_name(dummy_d) + " = " + ns.get_name(dummy_s) + ";\n"
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r += syn_on
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r += "end\n"
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r += "\n"
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@@ -275,7 +294,7 @@ def _printinit(f, ios, ns):
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signals = (list_signals(f) | list_special_ios(f, True, False, False)) \
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- ios \
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- list_targets(f) \
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- - list_special_ios(f, False, True, True)
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+ - list_special_ios(f, False, True, False)
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if signals:
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r += "initial begin\n"
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for s in sorted(signals, key=lambda x: x.huid):
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@@ -303,7 +322,7 @@ def convert(f, ios=None, name="top",
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ios |= {cd.clk, cd.rst}
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else:
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raise KeyError("Unresolved clock domain: '"+cd_name+"'")
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-
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+
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f = lower_complex_slices(f)
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insert_resets(f)
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f = lower_basics(f)
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--
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1.8.0.msysgit.0
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