toolchain: implement generic toolchain and devices toolchain refactoring
This commit is contained in:
Gwenhael Goavec-Merou
Florent Kermarrec
parent
ee1af96ab7
commit
9db1d9e49f
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@ -15,11 +15,27 @@ from shutil import which
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from migen.fhdl.structure import _Fragment
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from litex.build.generic_platform import Pins, IOStandard, Misc
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from litex.build.generic_toolchain import GenericToolchain
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from litex.build import tools
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# AlteraQuartusToolchain ---------------------------------------------------------------------------
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class AlteraQuartusToolchain(GenericToolchain):
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attr_translate = {}
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def __init__(self):
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super().__init__()
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self.additional_sdc_commands = []
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self.additional_qsf_commands = []
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self.cst = []
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def build(self, platform, fragment, **kwargs):
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return self._build(platform, fragment, **kwargs)
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# IO/Placement Constraints (.qsf) ------------------------------------------------------------------
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def _format_constraint(c, signame, fmt_r):
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def _format_constraint(self, c, signame, fmt_r):
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# IO location constraints
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if isinstance(c, Pins):
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tpl = "set_location_assignment -comment \"{name}\" -to {signame} Pin_{pin}"
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@ -39,14 +55,14 @@ def _format_constraint(c, signame, fmt_r):
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tpl = "set_instance_assignment -comment \"{name}\" -name {misc} -to {signame}"
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return tpl.format(signame=signame, name=fmt_r, misc=c.misc)
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def _format_qsf_constraint(signame, pin, others, resname):
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def _format_qsf_constraint(self, signame, pin, others, resname):
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fmt_r = "{}:{}".format(*resname[:2])
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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fmt_c = [_format_constraint(c, signame, fmt_r) for c in ([Pins(pin)] + others)]
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fmt_c = [self._format_constraint(c, signame, fmt_r) for c in ([Pins(pin)] + others)]
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return '\n'.join(fmt_c)
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def _is_virtual_pin(pin_name):
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def _is_virtual_pin(self, pin_name):
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return pin_name in (
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"altera_reserved_tms",
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"altera_reserved_tck",
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@ -54,31 +70,29 @@ def _is_virtual_pin(pin_name):
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"altera_reserved_tdo",
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)
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def _build_qsf_constraints(named_sc, named_pc):
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qsf = []
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def build_constr_file(self, named_sc, named_pc):
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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if _is_virtual_pin(p):
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if self._is_virtual_pin(p):
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continue
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qsf.append(_format_qsf_constraint("{}[{}]".format(sig, i), p, others, resname))
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self.cst.append(self._format_qsf_constraint("{}[{}]".format(sig, i), p, others, resname))
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else:
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if _is_virtual_pin(pins[0]):
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if self._is_virtual_pin(pins[0]):
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continue
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qsf.append(_format_qsf_constraint(sig, pins[0], others, resname))
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self.cst.append(self._format_qsf_constraint(sig, pins[0], others, resname))
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if named_pc:
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qsf.append("\n\n".join(named_pc))
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return "\n".join(qsf)
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self.cst.append("\n\n".join(named_pc))
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# Timing Constraints (.sdc) ------------------------------------------------------------------------
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def _build_sdc(clocks, false_paths, vns, named_sc, build_name, additional_sdc_commands):
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def build_timing_constr(self, vns, clocks):
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sdc = []
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# Clock constraints
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for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
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is_port = False
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for sig, pins, others, resname in named_sc:
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for sig, pins, others, resname in self.named_sc:
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if sig == vns.get_name(clk):
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is_port = True
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if is_port:
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@ -92,26 +106,26 @@ def _build_sdc(clocks, false_paths, vns, named_sc, build_name, additional_sdc_co
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sdc.append("derive_pll_clocks")
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# False path constraints
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for from_, to in sorted(false_paths, key=lambda x: (x[0].duid, x[1].duid)):
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for from_, to in sorted(self.false_paths, key=lambda x: (x[0].duid, x[1].duid)):
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tpl = "set_false_path -from [get_clocks {{{from_}}}] -to [get_clocks {{{to}}}]"
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sdc.append(tpl.format(from_=vns.get_name(from_), to=vns.get_name(to)))
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# Add additional commands
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sdc += additional_sdc_commands
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sdc += self.additional_sdc_commands
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# Generate .sdc
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tools.write_to_file("{}.sdc".format(build_name), "\n".join(sdc))
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tools.write_to_file("{}.sdc".format(self._build_name), "\n".join(sdc))
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# Project (.qsf) -----------------------------------------------------------------------------------
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def _build_qsf(device, ips, sources, vincpaths, named_sc, named_pc, build_name, additional_qsf_commands):
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def build_project(self):
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qsf = []
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# Set device
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qsf.append("set_global_assignment -name DEVICE {}".format(device))
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qsf.append("set_global_assignment -name DEVICE {}".format(self.platform.device))
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# Add sources
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for filename, language, library, *copy in sources:
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for filename, language, library, *copy in self.platform.sources:
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if language == "verilog": language = "systemverilog" # Enforce use of SystemVerilog
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tpl = "set_global_assignment -name {lang}_FILE {path} -library {lib}"
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# Do not add None type files
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@ -122,36 +136,40 @@ def _build_qsf(device, ips, sources, vincpaths, named_sc, named_pc, build_name,
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else:
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if filename.endswith(".svh") or filename.endswith(".vh"):
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fpath = os.path.dirname(filename)
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if fpath not in vincpaths:
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vincpaths.append(fpath)
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if fpath not in platform.verilog_include_paths:
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platform.verilog_include_paths.append(fpath)
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# Add ips
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for filename in ips:
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for filename in self.platform.ips:
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tpl = "set_global_assignment -name QSYS_FILE {filename}"
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qsf.append(tpl.replace(filename=filename.replace("\\", "/")))
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# Add include paths
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for path in vincpaths:
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for path in self.platform.verilog_include_paths:
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qsf.append("set_global_assignment -name SEARCH_PATH {}".format(path.replace("\\", "/")))
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# Set top level
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qsf.append("set_global_assignment -name top_level_entity " + build_name)
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qsf.append("set_global_assignment -name top_level_entity " + self._build_name)
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# Add io, placement constraints
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qsf.append(_build_qsf_constraints(named_sc, named_pc))
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qsf.append("\n".join(self.cst))
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# Set timing constraints
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qsf.append("set_global_assignment -name SDC_FILE {}.sdc".format(build_name))
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qsf.append("set_global_assignment -name SDC_FILE {}.sdc".format(self._build_name))
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# Add additional commands
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qsf += additional_qsf_commands
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qsf += self.additional_qsf_commands
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# Generate .qsf
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tools.write_to_file("{}.qsf".format(build_name), "\n".join(qsf))
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tools.write_to_file("{}.qsf".format(self._build_name), "\n".join(qsf))
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# Script -------------------------------------------------------------------------------------------
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def _build_script(build_name, create_rbf):
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def build_script(self):
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build_name = self._build_name
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self._build_qsf()
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if sys.platform in ["win32", "cygwin"]:
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script_file = "build_" + build_name + ".bat"
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script_contents = "REM Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n"
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@ -165,7 +183,7 @@ quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c
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quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
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quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
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quartus_sta {build_name} -c {build_name}"""
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if create_rbf:
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if self.platform.create_rbf:
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if sys.platform in ["win32", "cygwin"]:
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script_contents += """
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if exist "{build_name}.sof" (
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@ -184,7 +202,7 @@ fi
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return script_file
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def _run_script(script):
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def run_script(self, script):
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if sys.platform in ["win32", "cygwin"]:
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shell = ["cmd", "/c"]
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else:
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@ -198,71 +216,6 @@ def _run_script(script):
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if subprocess.call(shell + [script]) != 0:
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raise OSError("Error occured during Quartus's script execution.")
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# AlteraQuartusToolchain ---------------------------------------------------------------------------
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class AlteraQuartusToolchain:
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attr_translate = {}
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def __init__(self):
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self.clocks = dict()
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self.false_paths = set()
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self.additional_sdc_commands = []
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self.additional_qsf_commands = []
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def build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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run = True,
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**kwargs):
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# Create build directory
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cwd = os.getcwd()
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Generate verilog
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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# Generate design timing constraints file (.sdc)
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_build_sdc(
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clocks = self.clocks,
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false_paths = self.false_paths,
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vns = v_output.ns,
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named_sc = named_sc,
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build_name = build_name,
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additional_sdc_commands = self.additional_sdc_commands)
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# Generate design project and location constraints file (.qsf)
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_build_qsf(
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device = platform.device,
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ips = platform.ips,
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sources = platform.sources,
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vincpaths = platform.verilog_include_paths,
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named_sc = named_sc,
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named_pc = named_pc,
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build_name = build_name,
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additional_qsf_commands = self.additional_qsf_commands)
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# Generate build script
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script = _build_script(build_name, platform.create_rbf)
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# Run
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if run:
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_run_script(script)
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os.chdir(cwd)
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return v_output.ns
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def add_period_constraint(self, platform, clk, period):
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clk.attr.add("keep")
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period = math.floor(period*1e3)/1e3 # round to lowest picosecond
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@ -0,0 +1,96 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2017-2018 William D. Jones <thor0505@comcast.net>
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import sys
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import subprocess
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from shutil import which
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from migen.fhdl.structure import _Fragment
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from litex.build.generic_platform import *
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from litex.build import tools
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# GenericToolchain -------------------------------------------------------------------------
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class GenericToolchain:
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attr_translate = {
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"keep": ("keep", "true"),
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}
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def __init__(self):
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self.clocks = dict()
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self.false_paths = set() # FIXME: use it
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self.named_pc = []
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self.named_sc = []
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# method use to build timing params
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def build_timing_constr(self, vns, clocks):
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pass
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# method use to build project (if required)
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def build_timing_constr(self, vns, clocks):
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pass
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def _build(self, platform, fragment,
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build_dir = "build",
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build_name = "top",
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synth_opts = "",
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run = True,
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**kwargs):
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self._build_name = build_name
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self._synth_opts = synth_opts
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self.platform = platform
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# Create build directory
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Generate verilog
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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self.named_sc, self.named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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v_output.write(v_file)
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platform.add_source(v_file)
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# Generate design io constraints file
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self.build_constr_file(self.named_sc, self.named_pc)
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# Generate design timing constraints file (in timing_constr file)
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self.build_timing_constr(v_output.ns, self.clocks)
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# Generate project
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self.build_project()
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# Generate build script
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script = self.build_script()
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# Run
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if run:
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self.run_script(script)
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os.chdir(cwd)
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return v_output.ns
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def add_period_constraint(self, platform, clk, period):
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clk.attr.add("keep")
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if clk in self.clocks:
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if period != self.clocks[clk]:
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raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
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.format(self.clocks[clk], period))
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self.clocks[clk] = period
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@ -16,10 +16,37 @@ from migen.fhdl.structure import _Fragment
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from litex.build.generic_platform import *
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from litex.build import tools
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from litex.build.lattice import common
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from litex.build.generic_toolchain import GenericToolchain
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# IO Constraints (.pcf) ----------------------------------------------------------------------------
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# LatticeIceStormToolchain -------------------------------------------------------------------------
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def _build_pcf(named_sc, named_pc):
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class LatticeIceStormToolchain(GenericToolchain):
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attr_translate = {
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"keep": ("keep", "true"),
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}
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special_overrides = common.lattice_ice40_special_overrides
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def __init__(self):
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super().__init__()
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self.yosys_template = self._yosys_template
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self.build_template = self._build_template
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def build(self, platform, fragment,
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timingstrict = False,
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ignoreloops = False,
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seed = 1,
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**kwargs):
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self.timingstrict = timingstrict
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self.ignoreloops = ignoreloops
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self.seed = seed
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return self._build(platform, fragment, **kwargs)
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# IO Constraints (.pcf) ------------------------------------------------------------------------
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def build_constr_file(self, named_sc, named_pc):
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r = ""
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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@ -29,18 +56,33 @@ def _build_pcf(named_sc, named_pc):
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r += "set_io {} {}\n".format(sig, pins[0])
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if named_pc:
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r += "\n" + "\n\n".join(named_pc)
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return r
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tools.write_to_file(self._build_name + "pcf", r)
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# Timing Constraints (in pre_pack file) ------------------------------------------------------------
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def _build_pre_pack(vns, clocks):
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def build_timing_constr(self, vns, clocks):
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r = ""
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for clk, period in clocks.items():
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r += """ctx.addClock("{}", {})\n""".format(vns.get_name(clk), 1e3/period)
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return r
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tools.write_to_file(self._build_name + "_pre_pack.py", r)
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# Yosys/Nextpnr Helpers/Templates ------------------------------------------------------------------
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def _yosys_import_sources(self):
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includes = ""
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reads = []
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for path in self.platform.verilog_include_paths:
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includes += " -I" + path
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for filename, language, library, *copy in self.platform.sources:
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# yosys has no such function read_systemverilog
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if language == "systemverilog":
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language = "verilog -sv"
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reads.append("read_{}{} {}".format(
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language, includes, filename))
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return "\n".join(reads)
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# Project (ys) -------------------------------------------------------------------------------------
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_yosys_template = [
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"verilog_defaults -push",
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"verilog_defaults -add -defer",
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@ -50,51 +92,15 @@ _yosys_template = [
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"synth_ice40 {synth_opts} -json {build_name}.json -top {build_name} -dsp",
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]
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def _yosys_import_sources(platform):
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includes = ""
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reads = []
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for path in platform.verilog_include_paths:
|
||||
includes += " -I" + path
|
||||
for filename, language, library, *copy in platform.sources:
|
||||
# yosys has no such function read_systemverilog
|
||||
if language == "systemverilog":
|
||||
language = "verilog -sv"
|
||||
reads.append("read_{}{} {}".format(
|
||||
language, includes, filename))
|
||||
return "\n".join(reads)
|
||||
|
||||
def _build_yosys(template, platform, build_name, synth_opts):
|
||||
def build_project(self):
|
||||
ys = []
|
||||
for l in template:
|
||||
for l in self._yosys_template:
|
||||
ys.append(l.format(
|
||||
build_name = build_name,
|
||||
read_files = _yosys_import_sources(platform),
|
||||
synth_opts = synth_opts
|
||||
build_name = self._build_name,
|
||||
read_files = self._yosys_import_sources(),
|
||||
synth_opts = self._synth_opts
|
||||
))
|
||||
tools.write_to_file(build_name + ".ys", "\n".join(ys))
|
||||
|
||||
def parse_device(device):
|
||||
packages = {
|
||||
"lp384": ["qn32", "cm36", "cm49"],
|
||||
"lp1k": ["swg16tr", "cm36", "cm49", "cm81", "cb81", "qn84", "cm121", "cb121"],
|
||||
"hx1k": ["vq100", "cb132", "tq144"],
|
||||
"lp8k": ["cm81", "cm81:4k", "cm121", "cm121:4k", "cm225", "cm225:4k"],
|
||||
"hx8k": ["bg121", "bg121:4k", "cb132", "cb132:4k", "cm121",
|
||||
"cm121:4k", "cm225", "cm225:4k", "cm81", "cm81:4k",
|
||||
"ct256", "tq144:4k"],
|
||||
"up3k": ["sg48", "uwg30"],
|
||||
"up5k": ["sg48", "uwg30"],
|
||||
"u4k": ["sg48"],
|
||||
}
|
||||
|
||||
(family, architecture, package) = device.split("-")
|
||||
if family not in ["ice40"]:
|
||||
raise ValueError("Unknown device family {}".format(family))
|
||||
if architecture not in packages.keys():
|
||||
raise ValueError("Invalid device architecture {}".format(architecture))
|
||||
if package not in packages[architecture]:
|
||||
raise ValueError("Invalid device package {}".format(package))
|
||||
return (family, architecture, package)
|
||||
tools.write_to_file(self._build_name + ".ys", "\n".join(ys))
|
||||
|
||||
# Script -------------------------------------------------------------------------------------------
|
||||
|
||||
|
|
@ -105,7 +111,10 @@ _build_template = [
|
|||
"icepack -s {build_name}.txt {build_name}.bin"
|
||||
]
|
||||
|
||||
def _build_script(build_template, build_name, architecture, package, timingstrict, ignoreloops, seed):
|
||||
def build_script(self):
|
||||
# Translate device to Nextpnr architecture/package
|
||||
(family, architecture, package) = self.parse_device()
|
||||
|
||||
if sys.platform in ("win32", "cygwin"):
|
||||
script_ext = ".bat"
|
||||
script_contents = "@echo off\nrem Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n\n"
|
||||
|
|
@ -115,23 +124,23 @@ def _build_script(build_template, build_name, architecture, package, timingstric
|
|||
script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
|
||||
fail_stmt = ""
|
||||
|
||||
for s in build_template:
|
||||
for s in self.build_template:
|
||||
s_fail = s + "{fail_stmt}\n" # Required so Windows scripts fail early.
|
||||
script_contents += s_fail.format(
|
||||
build_name = build_name,
|
||||
build_name = self._build_name,
|
||||
architecture = architecture,
|
||||
package = package,
|
||||
timefailarg = "--timing-allow-fail" if not timingstrict else "",
|
||||
ignoreloops = "--ignore-loops" if ignoreloops else "",
|
||||
timefailarg = "--timing-allow-fail" if not self.timingstrict else "",
|
||||
ignoreloops = "--ignore-loops" if self.ignoreloops else "",
|
||||
fail_stmt = fail_stmt,
|
||||
seed = seed)
|
||||
seed = self.seed)
|
||||
|
||||
script_file = "build_" + build_name + script_ext
|
||||
script_file = "build_" + self._build_name + script_ext
|
||||
tools.write_to_file(script_file, script_contents, force_unix=False)
|
||||
|
||||
return script_file
|
||||
|
||||
def _run_script(script):
|
||||
def run_script(script):
|
||||
if sys.platform in ("win32", "cygwin"):
|
||||
shell = ["cmd", "/c"]
|
||||
else:
|
||||
|
|
@ -145,77 +154,29 @@ def _run_script(script):
|
|||
if subprocess.call(shell + [script]) != 0:
|
||||
raise OSError("Error occured during Yosys/Nextpnr's script execution.")
|
||||
|
||||
# LatticeIceStormToolchain -------------------------------------------------------------------------
|
||||
|
||||
class LatticeIceStormToolchain:
|
||||
attr_translate = {
|
||||
"keep": ("keep", "true"),
|
||||
def parse_device(self):
|
||||
packages = {
|
||||
"lp384": ["qn32", "cm36", "cm49"],
|
||||
"lp1k": ["swg16tr", "cm36", "cm49", "cm81", "cb81", "qn84", "cm121", "cb121"],
|
||||
"hx1k": ["vq100", "cb132", "tq144"],
|
||||
"lp8k": ["cm81", "cm81:4k", "cm121", "cm121:4k", "cm225", "cm225:4k"],
|
||||
"hx8k": ["bg121", "bg121:4k", "cb132", "cb132:4k", "cm121",
|
||||
"cm121:4k", "cm225", "cm225:4k", "cm81", "cm81:4k",
|
||||
"ct256", "tq144:4k"],
|
||||
"up3k": ["sg48", "uwg30"],
|
||||
"up5k": ["sg48", "uwg30"],
|
||||
"u4k": ["sg48"],
|
||||
}
|
||||
|
||||
special_overrides = common.lattice_ice40_special_overrides
|
||||
(family, architecture, package) = self.platform.device.split("-")
|
||||
if family not in ["ice40"]:
|
||||
raise ValueError("Unknown device family {}".format(family))
|
||||
if architecture not in packages.keys():
|
||||
raise ValueError("Invalid device architecture {}".format(architecture))
|
||||
if package not in packages[architecture]:
|
||||
raise ValueError("Invalid device package {}".format(package))
|
||||
return (family, architecture, package)
|
||||
|
||||
def __init__(self):
|
||||
self.yosys_template = _yosys_template
|
||||
self.build_template = _build_template
|
||||
self.clocks = dict()
|
||||
|
||||
def build(self, platform, fragment,
|
||||
build_dir = "build",
|
||||
build_name = "top",
|
||||
synth_opts = "",
|
||||
run = True,
|
||||
timingstrict = False,
|
||||
ignoreloops = False,
|
||||
seed = 1,
|
||||
**kwargs):
|
||||
|
||||
# Create build directory
|
||||
os.makedirs(build_dir, exist_ok=True)
|
||||
cwd = os.getcwd()
|
||||
os.chdir(build_dir)
|
||||
|
||||
# Finalize design
|
||||
if not isinstance(fragment, _Fragment):
|
||||
fragment = fragment.get_fragment()
|
||||
platform.finalize(fragment)
|
||||
|
||||
# Generate verilog
|
||||
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
|
||||
named_sc, named_pc = platform.resolve_signals(v_output.ns)
|
||||
v_file = build_name + ".v"
|
||||
v_output.write(v_file)
|
||||
platform.add_source(v_file)
|
||||
|
||||
# Generate design io constraints file (.pcf)
|
||||
tools.write_to_file(build_name + ".pcf",_build_pcf(named_sc, named_pc))
|
||||
|
||||
# Generate design timing constraints file (in pre_pack file)
|
||||
tools.write_to_file(build_name + "_pre_pack.py", _build_pre_pack(v_output.ns, self.clocks))
|
||||
|
||||
# Generate Yosys script
|
||||
_build_yosys(self.yosys_template, platform, build_name, synth_opts=synth_opts)
|
||||
|
||||
# Translate device to Nextpnr architecture/package
|
||||
(family, architecture, package) = parse_device(platform.device)
|
||||
|
||||
# Generate build script
|
||||
script = _build_script(self.build_template, build_name, architecture, package, timingstrict, ignoreloops, seed)
|
||||
|
||||
# Run
|
||||
if run:
|
||||
_run_script(script)
|
||||
|
||||
os.chdir(cwd)
|
||||
|
||||
return v_output.ns
|
||||
|
||||
def add_period_constraint(self, platform, clk, period):
|
||||
clk.attr.add("keep")
|
||||
if clk in self.clocks:
|
||||
if period != self.clocks[clk]:
|
||||
raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
|
||||
.format(self.clocks[clk], period))
|
||||
self.clocks[clk] = period
|
||||
|
||||
def icestorm_args(parser):
|
||||
toolchain_group = parser.add_argument_group(title="Toolchain options")
|
||||
|
|
|
|||
|
|
@ -16,10 +16,48 @@ from migen.fhdl.structure import _Fragment
|
|||
from litex.build.generic_platform import *
|
||||
from litex.build import tools
|
||||
from litex.build.lattice import common
|
||||
from litex.build.generic_toolchain import GenericToolchain
|
||||
|
||||
# LatticeTrellisToolchain --------------------------------------------------------------------------
|
||||
|
||||
class LatticeTrellisToolchain(GenericToolchain):
|
||||
attr_translate = {
|
||||
"keep": ("keep", "true"),
|
||||
}
|
||||
|
||||
special_overrides = common.lattice_ecp5_trellis_special_overrides
|
||||
|
||||
def __init__(self):
|
||||
super().__init__()
|
||||
self.yosys_template = self._yosys_template
|
||||
self.build_template = self._build_template
|
||||
|
||||
def build(self, platform, fragment,
|
||||
nowidelut = False,
|
||||
abc9 = False,
|
||||
timingstrict = False,
|
||||
ignoreloops = False,
|
||||
bootaddr = 0,
|
||||
seed = 1,
|
||||
spimode = None,
|
||||
compress = True,
|
||||
**kwargs):
|
||||
|
||||
self._nowidelut = nowidelut
|
||||
self._abc9 = abc9
|
||||
self._timingstrict = timingstrict
|
||||
self._ignoreloops = ignoreloops
|
||||
self._bootaddr = bootaddr
|
||||
self._seed = seed
|
||||
self._spimode = spimode
|
||||
self._compress = compress
|
||||
|
||||
return self._build(platform, fragment, **kwargs)
|
||||
|
||||
# IO Constraints (.lpf) ----------------------------------------------------------------------------
|
||||
|
||||
def _format_constraint(c):
|
||||
@classmethod
|
||||
def _format_constraint(cls, c):
|
||||
if isinstance(c, Pins):
|
||||
return ("LOCATE COMP ", " SITE " + "\"" + c.identifiers[0] + "\"")
|
||||
elif isinstance(c, IOStandard):
|
||||
|
|
@ -27,28 +65,26 @@ def _format_constraint(c):
|
|||
elif isinstance(c, Misc):
|
||||
return ("IOBUF PORT ", " " + c.misc)
|
||||
|
||||
|
||||
def _format_lpf(signame, pin, others, resname):
|
||||
fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
|
||||
def _format_lpf(self, signame, pin, others, resname):
|
||||
fmt_c = [self._format_constraint(c) for c in ([Pins(pin)] + others)]
|
||||
lpf = []
|
||||
for pre, suf in fmt_c:
|
||||
lpf.append(pre + "\"" + signame + "\"" + suf + ";")
|
||||
return "\n".join(lpf)
|
||||
|
||||
|
||||
def _build_lpf(named_sc, named_pc, build_name):
|
||||
def build_constr_file(self, named_sc, named_pc):
|
||||
lpf = []
|
||||
lpf.append("BLOCK RESETPATHS;")
|
||||
lpf.append("BLOCK ASYNCPATHS;")
|
||||
for sig, pins, others, resname in named_sc:
|
||||
if len(pins) > 1:
|
||||
for i, p in enumerate(pins):
|
||||
lpf.append(_format_lpf(sig + "[" + str(i) + "]", p, others, resname))
|
||||
lpf.append(self._format_lpf(sig + "[" + str(i) + "]", p, others, resname))
|
||||
else:
|
||||
lpf.append(_format_lpf(sig, pins[0], others, resname))
|
||||
lpf.append(self._format_lpf(sig, pins[0], others, resname))
|
||||
if named_pc:
|
||||
lpf.append("\n\n".join(named_pc))
|
||||
tools.write_to_file(build_name + ".lpf", "\n".join(lpf))
|
||||
tools.write_to_file(self._build_name + ".lpf", "\n".join(lpf))
|
||||
|
||||
# Yosys/Nextpnr Helpers/Templates ------------------------------------------------------------------
|
||||
|
||||
|
|
@ -61,12 +97,12 @@ _yosys_template = [
|
|||
"synth_ecp5 {nwl} {abc} -json {build_name}.json -top {build_name}",
|
||||
]
|
||||
|
||||
def _yosys_import_sources(platform):
|
||||
def _yosys_import_sources(self):
|
||||
includes = ""
|
||||
reads = []
|
||||
for path in platform.verilog_include_paths:
|
||||
for path in self.platform.verilog_include_paths:
|
||||
includes += " -I" + path
|
||||
for filename, language, library, *copy in platform.sources:
|
||||
for filename, language, library, *copy in self.platform.sources:
|
||||
# yosys has no such function read_systemverilog
|
||||
if language == "systemverilog":
|
||||
language = "verilog -sv"
|
||||
|
|
@ -74,18 +110,18 @@ def _yosys_import_sources(platform):
|
|||
language, includes, filename))
|
||||
return "\n".join(reads)
|
||||
|
||||
def _build_yosys(template, platform, nowidelut, abc9, build_name):
|
||||
def _build_yosys(self):
|
||||
ys = []
|
||||
for l in template:
|
||||
for l in self._yosys_template:
|
||||
ys.append(l.format(
|
||||
build_name = build_name,
|
||||
nwl = "-nowidelut" if nowidelut else "",
|
||||
abc = "-abc9" if abc9 else "",
|
||||
read_files = _yosys_import_sources(platform)
|
||||
build_name = self._build_name,
|
||||
nwl = "-nowidelut" if self._nowidelut else "",
|
||||
abc = "-abc9" if self._abc9 else "",
|
||||
read_files = self._yosys_import_sources()
|
||||
))
|
||||
tools.write_to_file(build_name + ".ys", "\n".join(ys))
|
||||
tools.write_to_file(self._build_name + ".ys", "\n".join(ys))
|
||||
|
||||
def nextpnr_ecp5_parse_device(device):
|
||||
def nextpnr_ecp5_parse_device(self, device):
|
||||
device = device.lower()
|
||||
family = device.split("-")[0]
|
||||
size = device.split("-")[1]
|
||||
|
|
@ -129,7 +165,13 @@ _build_template = [
|
|||
"ecppack {build_name}.config --svf {build_name}.svf --bit {build_name}.bit --bootaddr {bootaddr} {spimode} {compress}"
|
||||
]
|
||||
|
||||
def _build_script(source, build_template, build_name, architecture, package, speed_grade, timingstrict, ignoreloops, bootaddr, seed, spimode, compress):
|
||||
def build_script(self):
|
||||
# Generate Yosys script
|
||||
self._build_yosys()
|
||||
# Translate device to Nextpnr architecture/package
|
||||
(family, size, speed_grade, package) = self.nextpnr_ecp5_parse_device(self.platform.device)
|
||||
architecture = self.nextpnr_ecp5_architectures[(family + "-" + size)]
|
||||
|
||||
if sys.platform in ("win32", "cygwin"):
|
||||
script_ext = ".bat"
|
||||
script_contents = "@echo off\nrem Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n\n"
|
||||
|
|
@ -139,27 +181,27 @@ def _build_script(source, build_template, build_name, architecture, package, spe
|
|||
script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
|
||||
fail_stmt = ""
|
||||
|
||||
for s in build_template:
|
||||
for s in self._build_template:
|
||||
s_fail = s + "{fail_stmt}\n" # Required so Windows scripts fail early.
|
||||
script_contents += s_fail.format(
|
||||
build_name = build_name,
|
||||
build_name = self._build_name,
|
||||
architecture = architecture,
|
||||
package = package,
|
||||
speed_grade = speed_grade,
|
||||
timefailarg = "--timing-allow-fail" if not timingstrict else "",
|
||||
ignoreloops = "--ignore-loops" if ignoreloops else "",
|
||||
bootaddr = bootaddr,
|
||||
timefailarg = "--timing-allow-fail" if not self._timingstrict else "",
|
||||
ignoreloops = "--ignore-loops" if self._ignoreloops else "",
|
||||
bootaddr = self._bootaddr,
|
||||
fail_stmt = fail_stmt,
|
||||
seed = seed,
|
||||
spimode = "" if spimode is None else "--spimode {}".format(spimode),
|
||||
compress = "" if not compress else "--compress")
|
||||
seed = self._seed,
|
||||
spimode = "" if self._spimode is None else f"--spimode {self._spimode}",
|
||||
compress = "" if not self._compress else "--compress")
|
||||
|
||||
script_file = "build_" + build_name + script_ext
|
||||
script_file = "build_" + self._build_name + script_ext
|
||||
tools.write_to_file(script_file, script_contents, force_unix=False)
|
||||
|
||||
return script_file
|
||||
|
||||
def _run_script(script):
|
||||
def run_script(script):
|
||||
if sys.platform in ("win32", "cygwin"):
|
||||
shell = ["cmd", "/c"]
|
||||
else:
|
||||
|
|
@ -173,72 +215,6 @@ def _run_script(script):
|
|||
if subprocess.call(shell + [script]) != 0:
|
||||
raise OSError("Error occured during Yosys/Nextpnr's script execution.")
|
||||
|
||||
# LatticeTrellisToolchain --------------------------------------------------------------------------
|
||||
|
||||
class LatticeTrellisToolchain:
|
||||
attr_translate = {
|
||||
"keep": ("keep", "true"),
|
||||
}
|
||||
|
||||
special_overrides = common.lattice_ecp5_trellis_special_overrides
|
||||
|
||||
def __init__(self):
|
||||
self.yosys_template = _yosys_template
|
||||
self.build_template = _build_template
|
||||
self.false_paths = set() # FIXME: use it
|
||||
|
||||
def build(self, platform, fragment,
|
||||
build_dir = "build",
|
||||
build_name = "top",
|
||||
run = True,
|
||||
nowidelut = False,
|
||||
abc9 = False,
|
||||
timingstrict = False,
|
||||
ignoreloops = False,
|
||||
bootaddr = 0,
|
||||
seed = 1,
|
||||
spimode = None,
|
||||
compress = True,
|
||||
**kwargs):
|
||||
|
||||
# Create build directory
|
||||
os.makedirs(build_dir, exist_ok=True)
|
||||
cwd = os.getcwd()
|
||||
os.chdir(build_dir)
|
||||
|
||||
# Finalize design
|
||||
if not isinstance(fragment, _Fragment):
|
||||
fragment = fragment.get_fragment()
|
||||
platform.finalize(fragment)
|
||||
|
||||
# Generate verilog
|
||||
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
|
||||
named_sc, named_pc = platform.resolve_signals(v_output.ns)
|
||||
top_file = build_name + ".v"
|
||||
v_output.write(top_file)
|
||||
platform.add_source(top_file)
|
||||
|
||||
# Generate design constraints file (.lpf)
|
||||
_build_lpf(named_sc, named_pc, build_name)
|
||||
|
||||
# Generate Yosys script
|
||||
_build_yosys(self.yosys_template, platform, nowidelut, abc9, build_name)
|
||||
|
||||
# Translate device to Nextpnr architecture/package/speed_grade
|
||||
(family, size, speed_grade, package) = nextpnr_ecp5_parse_device(platform.device)
|
||||
architecture = nextpnr_ecp5_architectures[(family + "-" + size)]
|
||||
|
||||
# Generate build script
|
||||
script = _build_script(False, self.build_template, build_name, architecture, package,
|
||||
speed_grade, timingstrict, ignoreloops, bootaddr, seed, spimode, compress)
|
||||
# Run
|
||||
if run:
|
||||
_run_script(script)
|
||||
|
||||
os.chdir(cwd)
|
||||
|
||||
return v_output.ns
|
||||
|
||||
def add_period_constraint(self, platform, clk, period):
|
||||
platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(
|
||||
freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
|
||||
|
|
|
|||
Loading…
Reference in New Issue