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lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)

This commit is contained in:
Florent Kermarrec 2015-03-03 09:02:53 +01:00
parent ff29c86fe1
commit 9df60bf98e
2 changed files with 17 additions and 7 deletions
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17
misoclib/mem/sdram/core/lasmicon/multiplexer.py
View File

@ -90,13 +90,13 @@ class _Steerer(Module):
class Multiplexer(Module, AutoCSR): class Multiplexer(Module, AutoCSR):
def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic, def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic,
with_bandwidth_measurement=False): with_bandwidth=False):
assert(phy.settings.nphases == len(dfi.phases)) assert(phy.settings.nphases == len(dfi.phases))
# Command choosing # Command choosing
requests = [bm.cmd for bm in bank_machines] requests = [bm.cmd for bm in bank_machines]
choose_cmd = _CommandChooser(requests) self.submodules.choose_cmd = choose_cmd = _CommandChooser(requests)
choose_req = _CommandChooser(requests) self.submodules.choose_req = choose_req = _CommandChooser(requests)
self.comb += [ self.comb += [
choose_cmd.want_reads.eq(0), choose_cmd.want_reads.eq(0),
choose_cmd.want_writes.eq(0) choose_cmd.want_writes.eq(0)
@ -106,7 +106,6 @@ class Multiplexer(Module, AutoCSR):
choose_cmd.want_cmds.eq(1), choose_cmd.want_cmds.eq(1),
choose_req.want_cmds.eq(1) choose_req.want_cmds.eq(1)
] ]
self.submodules += choose_cmd, choose_req
# Command steering # Command steering
nop = CommandRequest(geom_settings.mux_a, geom_settings.bank_a) nop = CommandRequest(geom_settings.mux_a, geom_settings.bank_a)
@ -212,5 +211,11 @@ class Multiplexer(Module, AutoCSR):
fsm.finalize() fsm.finalize()
self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"]) self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"])
if with_bandwidth_measurement: self.with_bandwidth = with_bandwidth
self.submodules.bandwidth = Bandwidth(choose_req.cmd)
def add_bandwidth(self):
self.with_bandwidth = True
def do_finalize(self):
if self.with_bandwidth:
self.submodules.bandwidth = Bandwidth(self.choose_req.cmd)

7
misoclib/soc/sdram.py
View File

@ -19,7 +19,8 @@ class SDRAMSoC(SoC):
def __init__(self, platform, clk_freq, def __init__(self, platform, clk_freq,
ramcon_type="lasmicon", ramcon_type="lasmicon",
with_l2=True, l2_size=8192, with_l2=True, l2_size=8192,
with_memtest=False, with_bandwidth=False, # specific to LASMICON,
with_memtest=False, # ignored for MINICON
**kwargs): **kwargs):
SoC.__init__(self, platform, clk_freq, **kwargs) SoC.__init__(self, platform, clk_freq, **kwargs)
self.ramcon_type = ramcon_type self.ramcon_type = ramcon_type
@ -28,6 +29,7 @@ class SDRAMSoC(SoC):
self.l2_size = l2_size self.l2_size = l2_size
self.with_memtest = with_memtest self.with_memtest = with_memtest
self.with_bandwidth = with_bandwidth or with_memtest
self._sdram_phy_registered = False self._sdram_phy_registered = False
@ -41,6 +43,9 @@ class SDRAMSoC(SoC):
# LASMICON frontend # LASMICON frontend
if self.ramcon_type == "lasmicon": if self.ramcon_type == "lasmicon":
if self.with_bandwidth:
self.sdram.controller.multiplexer.add_bandwidth()
if self.with_memtest: if self.with_memtest:
self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master()) self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master()) self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())