integration/soc: fix dma_bus typo.
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@ -922,7 +922,7 @@ class SoC(Module):
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if ((len(self.dma_bus.masters) == 1) and
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(len(self.dma_bus.slaves) == 1) and
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(next(iter(self.dma_bus.regions.values())).origin == 0)):
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self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint(
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self.submodules.dma_bus_interconnect = wishbone.InterconnectPointToPoint(
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master = next(iter(self.dma_bus.masters.values())),
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slave = next(iter(self.dma_bus.slaves.values())))
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# Otherwise, use InterconnectShared.
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@ -931,10 +931,10 @@ class SoC(Module):
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masters = self.dma_bus.masters.values(),
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slaves = [(self.dma_bus.regions[n].decoder(self.dma_bus), s) for n, s in self.dma_bus.slaves.items()],
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register = True)
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self.bus.logger.info("DMA Interconnect: {} ({} <-> {}).".format(
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colorer(self.dma_bus_interconnect.__class__.__name__),
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colorer(len(self.dma_bus.masters)),
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colorer(len(self.dma_bus.slaves))))
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self.bus.logger.info("DMA Interconnect: {} ({} <-> {}).".format(
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colorer(self.dma_bus_interconnect.__class__.__name__),
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colorer(len(self.dma_bus.masters)),
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colorer(len(self.dma_bus.slaves))))
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self.add_constant("CONFIG_CPU_HAS_DMA_BUS")
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# SoC CSR Interconnect ---------------------------------------------------------------------
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