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integration/soc: fix dma_bus typo.

This commit is contained in:
Florent Kermarrec 2020-07-27 11:06:09 +02:00
parent 1fdffdfd6b
commit 9e07623b61
1 changed files with 5 additions and 5 deletions
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10
litex/soc/integration/soc.py
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@ -922,7 +922,7 @@ class SoC(Module):
if ((len(self.dma_bus.masters) == 1) and if ((len(self.dma_bus.masters) == 1) and
(len(self.dma_bus.slaves) == 1) and (len(self.dma_bus.slaves) == 1) and
(next(iter(self.dma_bus.regions.values())).origin == 0)): (next(iter(self.dma_bus.regions.values())).origin == 0)):
self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint( self.submodules.dma_bus_interconnect = wishbone.InterconnectPointToPoint(
master = next(iter(self.dma_bus.masters.values())), master = next(iter(self.dma_bus.masters.values())),
slave = next(iter(self.dma_bus.slaves.values()))) slave = next(iter(self.dma_bus.slaves.values())))
# Otherwise, use InterconnectShared. # Otherwise, use InterconnectShared.
@ -931,10 +931,10 @@ class SoC(Module):
masters = self.dma_bus.masters.values(), masters = self.dma_bus.masters.values(),
slaves = [(self.dma_bus.regions[n].decoder(self.dma_bus), s) for n, s in self.dma_bus.slaves.items()], slaves = [(self.dma_bus.regions[n].decoder(self.dma_bus), s) for n, s in self.dma_bus.slaves.items()],
register = True) register = True)
self.bus.logger.info("DMA Interconnect: {} ({} <-> {}).".format( self.bus.logger.info("DMA Interconnect: {} ({} <-> {}).".format(
colorer(self.dma_bus_interconnect.__class__.__name__), colorer(self.dma_bus_interconnect.__class__.__name__),
colorer(len(self.dma_bus.masters)), colorer(len(self.dma_bus.masters)),
colorer(len(self.dma_bus.slaves)))) colorer(len(self.dma_bus.slaves))))
self.add_constant("CONFIG_CPU_HAS_DMA_BUS") self.add_constant("CONFIG_CPU_HAS_DMA_BUS")
# SoC CSR Interconnect --------------------------------------------------------------------- # SoC CSR Interconnect ---------------------------------------------------------------------