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integration/soc: fix dma_bus typo.

This commit is contained in:
Florent Kermarrec 2020-07-27 11:06:09 +02:00
parent 1fdffdfd6b
commit 9e07623b61
1 changed files with 5 additions and 5 deletions
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2
litex/soc/integration/soc.py
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@ -922,7 +922,7 @@ class SoC(Module):
if ((len(self.dma_bus.masters) == 1) and
(len(self.dma_bus.slaves) == 1) and
(next(iter(self.dma_bus.regions.values())).origin == 0)):
self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint(
self.submodules.dma_bus_interconnect = wishbone.InterconnectPointToPoint(
master = next(iter(self.dma_bus.masters.values())),
slave = next(iter(self.dma_bus.slaves.values())))
# Otherwise, use InterconnectShared.