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interconnect/csr_bus: remove 64-bit CSR bus alignment support (no longer supported in SoCs).

This commit is contained in:
Florent Kermarrec 2020-07-06 09:51:32 +02:00
parent 527798f734
commit 9e46195299
1 changed files with 9 additions and 17 deletions
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26
litex/soc/interconnect/csr_bus.py
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@ -120,15 +120,11 @@ class SRAM(Module):
sel_r = Signal() sel_r = Signal()
self.sync += sel_r.eq(sel) self.sync += sel_r.eq(sel)
self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address) self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
if bus.alignment == 64:
self.comb += If(self.bus.adr[0], sel.eq(0))
adr_shift = log2_int(bus.alignment//32)
if word_bits: if word_bits:
word_index = Signal(word_bits, reset_less=True) word_index = Signal(word_bits, reset_less=True)
word_expanded = Signal(csrw_per_memw*data_width) word_expanded = Signal(csrw_per_memw*data_width)
self.sync += word_index.eq(self.bus.adr[adr_shift:adr_shift+word_bits]) self.sync += word_index.eq(self.bus.adr[:word_bits])
self.comb += [ self.comb += [
word_expanded.eq(port.dat_r), word_expanded.eq(port.dat_r),
If(sel_r, If(sel_r,
@ -139,11 +135,11 @@ class SRAM(Module):
wregs = [] wregs = []
for i in range(csrw_per_memw-1): for i in range(csrw_per_memw-1):
wreg = Signal(data_width, reset_less=True) wreg = Signal(data_width, reset_less=True)
self.sync += If(sel & self.bus.we & (self.bus.adr[adr_shift:adr_shift+word_bits] == i), wreg.eq(self.bus.dat_w)) self.sync += If(sel & self.bus.we & (self.bus.adr[:word_bits] == i), wreg.eq(self.bus.dat_w))
wregs.append(wreg) wregs.append(wreg)
memword_chunks = [self.bus.dat_w] + list(reversed(wregs)) memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
self.comb += [ self.comb += [
port.we.eq(sel & self.bus.we & (self.bus.adr[adr_shift:adr_shift+word_bits] == csrw_per_memw - 1)), port.we.eq(sel & self.bus.we & (self.bus.adr[:word_bits] == csrw_per_memw - 1)),
port.dat_w.eq(Cat(*memword_chunks)) port.dat_w.eq(Cat(*memword_chunks))
] ]
else: else:
@ -155,10 +151,10 @@ class SRAM(Module):
] ]
if self._page is None: if self._page is None:
self.comb += port.adr.eq(self.bus.adr[adr_shift+word_bits:adr_shift+word_bits+len(port.adr)]) self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+len(port.adr)])
else: else:
pv = self._page.storage pv = self._page.storage
self.comb += port.adr.eq(Cat(self.bus.adr[adr_shift+word_bits:adr_shift+word_bits+len(port.adr)-len(pv)], pv)) self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+len(port.adr)-len(pv)], pv))
def get_csrs(self): def get_csrs(self):
if self._page is None: if self._page is None:
@ -181,26 +177,22 @@ class CSRBank(csr.GenericBank):
sel = Signal() sel = Signal()
self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address) self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
if bus.alignment == 64:
self.comb += If(self.bus.adr[0], sel.eq(0))
adr_shift = log2_int(bus.alignment//soc_bus_data_width)
for i, c in enumerate(self.simple_csrs): for i, c in enumerate(self.simple_csrs):
self.comb += [ self.comb += [
c.r.eq(self.bus.dat_w[:c.size]), c.r.eq(self.bus.dat_w[:c.size]),
c.re.eq(sel & \ c.re.eq(sel & \
self.bus.we & \ self.bus.we & \
(self.bus.adr[adr_shift:adr_shift+self.decode_bits] == i)), (self.bus.adr[:self.decode_bits] == i)),
c.we.eq(sel & \ c.we.eq(sel & \
~self.bus.we & \ ~self.bus.we & \
(self.bus.adr[adr_shift:adr_shift+self.decode_bits] == i)), (self.bus.adr[:self.decode_bits] == i)),
] ]
brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs)) brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
self.sync += [ self.sync += [
self.bus.dat_r.eq(0), self.bus.dat_r.eq(0),
If(sel, Case(self.bus.adr[adr_shift:adr_shift+self.decode_bits], brcases)) If(sel, Case(self.bus.adr[:self.decode_bits], brcases))
] ]