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fix DDR3 on arty

This commit is contained in:
Felix Held 2018-01-12 13:54:10 +11:00
parent 7b6ba372c8
commit 9eb1beea04
1 changed files with 2 additions and 0 deletions
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2
litex/boards/targets/arty.py
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@ -108,6 +108,8 @@ class BaseSoC(SoCSDRAM):
# sdram # sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
sdram_module = MT41K128M16(self.clk_freq, "1:4") sdram_module = MT41K128M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.geom_settings,