fix DDR3 on arty

2018-01-12 13:54:10 +11:00 · 2018-01-12 13:54:10 +11:00 · 9eb1beea04
parent 7b6ba372c8
commit 9eb1beea04
1 changed files with 2 additions and 0 deletions
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@ -108,6 +108,8 @@ class BaseSoC(SoCSDRAM):

        # sdram
        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        self.add_constant("READ_LEVELING_BITSLIP", 3)
+        self.add_constant("READ_LEVELING_DELAY", 14)
        sdram_module = MT41K128M16(self.clk_freq, "1:4")
        self.register_sdram(self.ddrphy,
                            sdram_module.geom_settings,