mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
dvisampler: add clocking and phase detector
This commit is contained in:
Sebastien Bourdeauducq
parent
0168f83523
commit
9f02ced39e
4 changed files with 226 additions and 9 deletions
11
build.py
11
build.py
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@ -43,10 +43,19 @@ TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
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NET "asfifo*/counter_read/gray_count*" TIG;
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NET "asfifo*/counter_write/gray_count*" TIG;
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NET "asfifo*/preset_empty*" TIG;
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NET "{dviclk0}" TNM_NET = "GRPdviclk0";
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NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
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TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 22 ns HIGH 50%;
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NET "{dviclk1}" TNM_NET = "GRPdviclk1";
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NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;
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TIMESPEC "TSdviclk1" = PERIOD "GRPdviclk1" 22 ns HIGH 50%;
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""",
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clk50=soc.crg.clk50_pad,
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phy_rx_clk=soc.crg.eth_rx_clk_pad,
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phy_tx_clk=soc.crg.eth_tx_clk_pad)
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phy_tx_clk=soc.crg.eth_tx_clk_pad,
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dviclk0=soc.dvisampler0.clk,
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dviclk1=soc.dvisampler1.clk)
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# add Verilog sources
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for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]:
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@ -3,16 +3,28 @@ from migen.fhdl.module import Module
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from migen.bank.description import *
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.datacapture import DataCapture
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class DVISampler(Module, AutoReg):
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def __init__(self, inversions=""):
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self.clk = Signal()
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for datan in "012":
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name = "data" + str(datan)
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if datan in inversions:
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name += "_n"
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setattr(self, name, Signal(name=name))
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def __init__(self, inversions="", debug_data_capture=True):
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self.submodules.edid = EDID()
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self.sda = self.edid.sda
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self.scl = self.edid.scl
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self.submodules.clocking = Clocking()
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self.clk = self.clocking.clkin
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for datan in "012":
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name = "data" + str(datan)
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cap = DataCapture(8, debug_data_capture)
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setattr(self.submodules, name + "_cap", cap)
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if datan in inversions:
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name += "_n"
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s = Signal(name=name)
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setattr(self, name, s)
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self.comb += [
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cap.pad.eq(s),
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cap.serdesstrobe.eq(self.clocking.serdesstrobe),
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cap.delay_rst.eq(~self.clocking.locked)
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]
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60
milkymist/dvisampler/clocking.py
Normal file
60
milkymist/dvisampler/clocking.py
Normal file
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@ -0,0 +1,60 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Instance
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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class Clocking(Module, AutoReg):
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def __init__(self):
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self.clkin = Signal()
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self._r_pll_reset = RegisterField(reset=1)
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self._r_locked = RegisterField(1, READ_ONLY, WRITE_ONLY)
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self.locked = Signal()
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self.serdesstrobe = Signal()
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self._cd_pix = ClockDomain()
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self._cd_pix5x = ClockDomain()
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self._cd_pix20x = ClockDomain()
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###
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clkfbout = Signal()
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pll_locked = Signal()
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pll_clk0 = Signal()
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pll_clk1 = Signal()
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pll_clk2 = Signal()
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self.specials += Instance("PLL_BASE",
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Instance.Parameter("CLKIN_PERIOD", 22.0),
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Instance.Parameter("CLKFBOUT_MULT", 20),
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Instance.Parameter("CLKOUT0_DIVIDE", 20), # pix
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Instance.Parameter("CLKOUT1_DIVIDE", 4), # pix5x
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Instance.Parameter("CLKOUT2_DIVIDE", 1), # pix20x
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Instance.Parameter("COMPENSATION", "INTERNAL"),
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Instance.Output("CLKFBOUT", clkfbout),
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Instance.Output("CLKOUT0", pll_clk0),
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Instance.Output("CLKOUT1", pll_clk1),
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Instance.Output("CLKOUT2", pll_clk2),
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Instance.Output("LOCKED", pll_locked),
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Instance.Input("CLKFBIN", clkfbout),
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Instance.Input("CLKIN", self.clkin),
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Instance.Input("RST", self._r_pll_reset.field.r)
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)
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self.specials += Instance("BUFG",
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Instance.Input("I", pll_clk0), Instance.Output("O", self._cd_pix.clk))
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self.specials += Instance("BUFG",
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Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
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locked_async = Signal()
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self.specials += Instance("BUFPLL",
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Instance.Parameter("DIVIDE", 4),
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Instance.Input("PLLIN", pll_clk2),
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Instance.ClockPort("GCLK", "pix5x"),
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Instance.Input("LOCKED", pll_locked),
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Instance.Output("IOCLK", self._cd_pix20x.clk),
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Instance.Output("LOCK", locked_async),
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Instance.Output("SERDESSTROBE", self.serdesstrobe)
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)
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self.specials += MultiReg(locked_async, self.locked, "sys")
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self.comb += self._r_locked.field.w.eq(self.locked)
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136
milkymist/dvisampler/datacapture.py
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136
milkymist/dvisampler/datacapture.py
Normal file
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@ -0,0 +1,136 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Instance
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from migen.genlib.cdc import PulseSynchronizer
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from migen.bank.description import *
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class DataCapture(Module, AutoReg):
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def __init__(self, ntbits, debug=False):
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self.pad = Signal()
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self.serdesstrobe = Signal()
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self.delay_rst = Signal() # system clock domain
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self.d0 = Signal() # pix5x clock domain
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self.d1 = Signal() # pix5x clock domain
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if debug:
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self._r_delay_rst = RegisterRaw()
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self._r_current_tap = RegisterField(8, READ_ONLY, WRITE_ONLY)
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###
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# IO
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pad_delayed = Signal()
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delay_inc = Signal()
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delay_ce = Signal()
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delay_rst = Signal()
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delay_init = Signal()
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self.specials += Instance("IDELAY2",
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Instance.Parameter("DELAY_SRC", "IDATAIN"),
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Instance.Parameter("IDELAY_TYPE", "VARIABLE_FROM_ZERO"),
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Instance.Parameter("COUNTER_WRAP_AROUND", "STAY_AT_LIMIT"),
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Instance.Input("IDATAIN", self.pad),
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Instance.Output("DATAOUT", pad_delayed),
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Instance.Input("INC", delay_inc | delay_init),
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Instance.Input("CE", delay_ce | delay_init),
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Instance.Input("RST", delay_rst),
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Instance.ClockPort("CLK"),
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Instance.Input("CAL", 0),
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Instance.Input("T", 1)
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)
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# initialize delay to 127 taps
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delay_init_count = Signal(7, reset=127)
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self.comb += delay_init.eq(delay_init_count != 0)
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self.sync += If(delay_rst,
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delay_init_count.eq(127)
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).Elif(delay_init,
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delay_init_count.eq(delay_init_count - 1)
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)
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d0p = Signal()
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d1p = Signal()
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self.specials += Instance("ISERDES2",
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Instance.Parameter("BITSLIP_ENABLE", "FALSE"),
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Instance.Parameter("DATA_RATE", "SDR"),
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Instance.Parameter("DATA_WIDTH", 4),
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Instance.Parameter("INTERFACE_TYPE", "RETIMED"),
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Instance.Parameter("SERDES_MODE", "NONE"),
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Instance.Output("Q4", self.d0),
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Instance.Output("Q3", d0p),
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Instance.Output("Q2", self.d1),
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Instance.Output("Q1", d1p),
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Instance.Input("BITSLIP", 0),
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Instance.Input("CE0", 1),
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Instance.ClockPort("CLK0", "pix20x"),
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Instance.ClockPort("CLKDIV", "pix5x"),
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Instance.Input("D", pad_delayed),
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Instance.Input("IOCE", self.serdesstrobe),
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Instance.Input("RST", 0)
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)
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# Transition counter
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transitions = Signal(ntbits)
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lateness = Signal((ntbits + 1, True))
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pulse_inc = Signal()
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pulse_dec = Signal()
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self.sync.pix5x += [
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pulse_inc.eq(0),
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pulse_dec.eq(0),
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If(transitions == 2**ntbits - 1,
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If(lateness[ntbits],
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pulse_inc.eq(1)
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).Else(
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pulse_dec.eq(1)
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),
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lateness.eq(0),
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transitions.eq(0)
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).Elif(self.d0 != self.d1,
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If(self.d0,
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# 1 -----> 0
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# d0p
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If(d0p,
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lateness.eq(lateness - 1)
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).Else(
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lateness.eq(lateness + 1)
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)
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).Else(
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# 0 -----> 1
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# d0p
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If(d0p,
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lateness.eq(lateness + 1)
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).Else(
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lateness.eq(lateness - 1)
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)
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),
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transitions.eq(transitions + 1)
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)
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]
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# Send delay update commands to system (IDELAY) clock domain
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self.submodules.xf_inc = PulseSynchronizer("pix5x", "sys")
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self.submodules.xf_dec = PulseSynchronizer("pix5x", "sys")
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self.comb += [
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self.xf_inc.i.eq(pulse_inc),
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delay_inc.eq(self.xf_inc.o),
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self.xf_dec.i.eq(pulse_dec),
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delay_ce.eq(self.xf_inc.o | self.xf_dec.o)
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]
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# Debug
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if debug:
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self.comb += delay_rst.eq(self.delay_rst | self._r_delay_rst.re)
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current_tap = self._r_current_tap.field.w
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If(delay_rst,
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current_tap.eq(0)
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).Elif(delay_ce,
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If(delay_inc,
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If(current_tap != 0xff,
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current_tap.eq(current_tap + 1)
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)
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).Else(
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If(current_tap != 0,
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current_tap.eq(current_tap - 1)
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)
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)
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)
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else:
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self.comb += delay_rst.eq(self.delay_rst)
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