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avalon/AvalonMM2Wishbone: Simplify wb.cti. 

In BURST-WRITE/READ, wb.cti can't be BURST_NONE.
This commit is contained in:
Florent Kermarrec 2023-05-08 09:42:12 +02:00
parent a62149831d
commit 9f44a498d6
1 changed files with 7 additions and 18 deletions
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25
litex/soc/interconnect/avalon/avalon_mm_to_wishbone.py
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@ -82,10 +82,9 @@ class AvalonMM2Wishbone(Module):
fsm.act("SINGLE",
burst_cycle.eq(0),
wb.sel.eq(avl.byteenable),
wb.cti.eq(wishbone.CTI_BURST_NONE),
If(avl.burstcount > 1,
wb.cti.eq(wishbone.CTI_BURST_INCREMENTING)
).Else(
wb.cti.eq(wishbone.CTI_BURST_NONE)
),
If(~avl.waitrequest & (avl.burstcount > 1),
burst_cycle.eq(1),
@ -101,14 +100,9 @@ class AvalonMM2Wishbone(Module):
fsm.act("BURST-WRITE",
burst_cycle.eq(1),
wb.sel.eq(burst_sel),
If(burst_counter > 1,
wb.cti.eq(wishbone.CTI_BURST_INCREMENTING)
).Else(
If(burst_counter == 1,
wb.cti.eq(wishbone.CTI_BURST_END)
).Else(
wb.cti.eq(wishbone.CTI_BURST_NONE)
)
wb.cti.eq(wishbone.CTI_BURST_INCREMENTING),
If(burst_counter == 1,
wb.cti.eq(wishbone.CTI_BURST_END)
),
If(~avl.waitrequest,
NextValue(burst_address, burst_address + word_width),
@ -124,14 +118,9 @@ class AvalonMM2Wishbone(Module):
burst_read.eq(1),
wb.stb.eq(1),
wb.sel.eq(burst_sel),
If(burst_counter > 1,
wb.cti.eq(wishbone.CTI_BURST_INCREMENTING),
).Else(
If(burst_counter == 1,
wb.cti.eq(wishbone.CTI_BURST_END)
).Else(
wb.cti.eq(wishbone.CTI_BURST_NONE)
)
wb.cti.eq(wishbone.CTI_BURST_INCREMENTING),
If(burst_counter == 1,
wb.cti.eq(wishbone.CTI_BURST_END)
),
If(wb.ack,
avl.readdatavalid.eq(1),