soc/cores/spi: Integrate SPIWishboneBridge from https://github.com/xobs/spibone.
"The ability to bridge Wishbone is an incredibly powerful one. However, the various bridges can be rather heavy in terms of resource usage. This presents a simple bridge that operates over SPI."
This commit is contained in:
Sean Cross
Florent Kermarrec
parent
f5c9425e14
commit
9f52ed1207
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.fhdl.specials import Tristate, TSTriple
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from migen.genlib.cdc import MultiReg
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from litex.soc.integration.doc import ModuleDoc, AutoDoc
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from litex.soc.interconnect import wishbone, stream
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class Spi4WireDocumentation(ModuleDoc):
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"""4-Wire SPI Protocol
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The 4-wire SPI protocol does not require any pins to change direction, and
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is therefore suitable for designs with level-shifters or without GPIOs that
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can change direction.
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While waiting for the response, the ``MISO`` line remains high. As soon as
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a response is available, the device pulls the `MISO` line low and clocks
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out either a ``0x00`` or `0x01` byte indicating whether it's a READ or a WRITE
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that is being answered. Note that if the operation is fast enough, the
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device will not pull the `MISO` line high and will immediately respond
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with ``0x00`` or ``0x01``.
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You can abort the operation by driving ``CS`` high. However, if a WRITE or
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READ has already been initiated then it will not be aborted.
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.. wavedrom::
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:caption: 4-Wire SPI Operation
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{ "signal": [
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["Read",
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{ "name": 'MOSI', "wave": 'x23...x|xxxxxx', "data": '0x01 [ADDRESS]'},
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{ "name": 'MISO', "wave": 'x.....x|25...x', "data": '0x01 [DATA]' },
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{ "name": 'CS', "wave": 'x0.....|.....x', "data": '1 2 3'},
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{ "name": 'data bits', "wave": 'xx2222x|x2222x', "data": '31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0'}
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],
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{},
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["Write",
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{ "name": 'MOSI', "wave": 'x23...3...x|xx', "data": '0x00 [ADDRESS] [DATA]'},
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{ "name": 'MISO', "wave": 'x.........1|2x', "data": '0x00' },
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{ "name": 'CS', "wave": 'x0.........|.x', "data": '1 2 3'},
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{ "name": 'data bits', "wave": 'xx22222222x|xx', "data": '31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0'}
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]
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]}
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"""
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class Spi3WireDocumentation(ModuleDoc):
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"""3-Wire SPI Protocol
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The 3-wire SPI protocol repurposes the ``MOSI`` line for both data input and
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data output. The direction of the line changes immediately after the
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address (for read) or the data (for write) and the device starts writing
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``0xFF``.
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As soon as data is available (read) or the data has been written (write),
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the device drives the ``MOSI`` line low in order to clock out ``0x00``
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or ``0x01``. This will always happen on a byte boundary.
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You can abort the operation by driving ``CS`` high. However, if a WRITE or
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READ has already been initiated then it will not be aborted.
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.. wavedrom::
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:caption: 3-Wire SPI Operation
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{ "signal": [
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["Read",
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{ "name": 'MOSI', "wave": 'x23...5|55...x', "data": '0x01 [ADDRESS] 0xFF 0x01 [DATA]'},
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{ "name": 'CS', "wave": 'x0.....|.....x', "data": '1 2 3'},
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{ "name": 'data bits', "wave": 'xx2222x|x2222x', "data": '31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0'}
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],
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{},
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["Write",
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{ "name": 'MOSI', "wave": 'x23...3...5|50', "data": '0x00 [ADDRESS] [DATA] 0xFF 0x00'},
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{ "name": 'CS', "wave": 'x0.........|.x', "data": '1 2 3'},
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{ "name": 'data bits', "wave": 'xx22222222x|xx', "data": '31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0'}
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]
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]}
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"""
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class Spi2WireDocumentation(ModuleDoc):
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"""2-Wire SPI Protocol
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The 2-wire SPI protocol removes the ``CS`` line in favor of a sync byte.
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Note that the 2-wire protocol has no way of interrupting communication,
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so if the bus locks up the device must be reset. The direction of the
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data line changes immediately after the address (for read) or the data
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(for write) and the device starts writing ``0xFF``.
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As soon as data is available (read) or the data has been written (write),
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the device drives the ``MOSI`` line low in order to clock out ``0x00``
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or ``0x01``. This will always happen on a byte boundary.
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All transactions begin with a sync byte of ``0xAB``.
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.. wavedrom::
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:caption: 2-Wire SPI Operation
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{ "signal": [
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["Write",
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{ "name": 'MOSI', "wave": '223...5|55...', "data": '0xAB 0x01 [ADDRESS] 0xFF 0x01 [DATA]'},
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{ "name": 'data bits', "wave": 'xx2222x|x2222', "data": '31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0'}
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],
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{},
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["Read",
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{ "name": 'MOSI', "wave": '223...3...5|5', "data": '0xAB 0x00 [ADDRESS] [DATA] 0xFF 0x00'},
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{ "name": 'data bits', "wave": 'xx22222222x|x', "data": '31:24 23:16 15:8 7:0 31:24 23:16 15:8 7:0'}
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]
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]}
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"""
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class SpiWishboneBridge(Module, ModuleDoc, AutoDoc):
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"""Wishbone Bridge over SPI
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This module allows for accessing a Wishbone bridge over a {}-wire protocol.
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All operations occur on byte boundaries, and are big-endian.
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The device can take a variable amount of time to respond, so the host should
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continue polling after the operation begins. If the Wishbone bus is
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particularly busy, such as during periods of heavy processing when the
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CPU's icache is empty, responses can take many thousands of cycles.
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The bridge core is designed to run at 1/4 the system clock.
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"""
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def __init__(self, pads, wires=4, with_tristate=True):
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self.wishbone = wishbone.Interface()
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# # #
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self.__doc__ = self.__doc__.format(wires)
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if wires == 4:
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self.mod_doc = Spi4WireDocumentation()
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elif wires == 3:
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self.mod_doc = Spi3WireDocumentation()
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elif wires == 2:
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self.mod_doc = Spi2WireDocumentation()
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clk = Signal()
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cs_n = Signal()
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mosi = Signal()
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miso = Signal()
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miso_en = Signal()
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counter = Signal(8)
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write_offset = Signal(5)
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command = Signal(8)
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address = Signal(32)
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value = Signal(32)
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wr = Signal()
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sync_byte = Signal(8)
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self.specials += [
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MultiReg(pads.clk, clk),
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]
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if wires == 2:
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io = TSTriple()
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self.specials += io.get_tristate(pads.mosi)
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self.specials += MultiReg(io.i, mosi)
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self.comb += io.o.eq(miso)
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self.comb += io.oe.eq(miso_en)
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elif wires == 3:
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self.specials += MultiReg(pads.cs_n, cs_n),
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io = TSTriple()
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self.specials += io.get_tristate(pads.mosi)
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self.specials += MultiReg(io.i, mosi)
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self.comb += io.o.eq(miso)
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self.comb += io.oe.eq(miso_en)
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elif wires == 4:
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self.specials += MultiReg(pads.cs_n, cs_n),
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self.specials += MultiReg(pads.mosi, mosi)
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if with_tristate:
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self.specials += Tristate(pads.miso, miso, ~cs_n)
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else:
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self.comb += pads.miso.eq(miso)
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else:
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raise ValueError("`wires` must be 2, 3, or 4")
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clk_last = Signal()
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clk_rising = Signal()
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clk_falling = Signal()
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self.sync += clk_last.eq(clk)
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self.comb += clk_rising.eq(clk & ~clk_last)
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self.comb += clk_falling.eq(~clk & clk_last)
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fsm = FSM(reset_state="IDLE")
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fsm = ResetInserter()(fsm)
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self.submodules += fsm
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self.comb += fsm.reset.eq(cs_n)
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# Connect the Wishbone bus up to our values
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self.comb += [
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self.wishbone.adr.eq(address[2:]),
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self.wishbone.dat_w.eq(value),
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self.wishbone.sel.eq(2**len(self.wishbone.sel) - 1)
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]
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# Constantly have the counter increase, except when it's reset
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# in the IDLE state
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self.sync += If(cs_n, counter.eq(0)).Elif(clk_rising, counter.eq(counter + 1))
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if wires == 2:
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fsm.act("IDLE",
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miso_en.eq(0),
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NextValue(miso, 1),
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If(clk_rising,
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NextValue(sync_byte, Cat(mosi, sync_byte))
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),
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If(sync_byte[0:7] == 0b101011,
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NextState("GET_TYPE_BYTE"),
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NextValue(counter, 0),
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NextValue(command, mosi),
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)
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)
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elif wires == 3 or wires == 4:
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fsm.act("IDLE",
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miso_en.eq(0),
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NextValue(miso, 1),
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If(clk_rising,
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NextState("GET_TYPE_BYTE"),
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NextValue(command, mosi),
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),
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)
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else:
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raise ValueError("invalid `wires` count: {}".format(wires))
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# Determine if it's a read or a write
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fsm.act("GET_TYPE_BYTE",
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miso_en.eq(0),
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NextValue(miso, 1),
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If(counter == 8,
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# Write value
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If(command == 0,
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NextValue(wr, 1),
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NextState("READ_ADDRESS"),
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# Read value
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).Elif(command == 1,
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NextValue(wr, 0),
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NextState("READ_ADDRESS"),
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).Else(
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NextState("END"),
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),
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),
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If(clk_rising,
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NextValue(command, Cat(mosi, command)),
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),
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)
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fsm.act("READ_ADDRESS",
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miso_en.eq(0),
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If(counter == 32 + 8,
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If(wr,
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NextState("READ_VALUE"),
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).Else(
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NextState("READ_WISHBONE"),
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)
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),
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If(clk_rising,
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NextValue(address, Cat(mosi, address)),
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),
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)
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fsm.act("READ_VALUE",
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miso_en.eq(0),
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If(counter == 32 + 32 + 8,
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NextState("WRITE_WISHBONE"),
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),
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If(clk_rising,
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NextValue(value, Cat(mosi, value)),
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),
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)
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fsm.act("WRITE_WISHBONE",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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miso_en.eq(1),
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If(self.wishbone.ack | self.wishbone.err,
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NextState("WAIT_BYTE_BOUNDARY"),
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),
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)
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fsm.act("READ_WISHBONE",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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miso_en.eq(1),
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If(self.wishbone.ack | self.wishbone.err,
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NextState("WAIT_BYTE_BOUNDARY"),
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NextValue(value, self.wishbone.dat_r),
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),
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)
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fsm.act("WAIT_BYTE_BOUNDARY",
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miso_en.eq(1),
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If(clk_falling,
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If(counter[0:3] == 0,
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NextValue(miso, 0),
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# For writes, fill in the 0 byte response
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If(wr,
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NextState("WRITE_WR_RESPONSE"),
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).Else(
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NextState("WRITE_RESPONSE"),
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),
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),
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),
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)
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# Write the "01" byte that indicates a response
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fsm.act("WRITE_RESPONSE",
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miso_en.eq(1),
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If(clk_falling,
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If(counter[0:3] == 0b111,
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NextValue(miso, 1),
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).Elif(counter[0:3] == 0,
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NextValue(write_offset, 31),
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NextState("WRITE_VALUE")
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),
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),
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)
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# Write the actual value
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fsm.act("WRITE_VALUE",
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miso_en.eq(1),
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NextValue(miso, value >> write_offset),
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If(clk_falling,
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NextValue(write_offset, write_offset - 1),
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If(write_offset == 0,
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NextValue(miso, 0),
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NextState("END"),
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),
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),
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)
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fsm.act("WRITE_WR_RESPONSE",
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miso_en.eq(1),
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If(clk_falling,
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If(counter[0:3] == 0,
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NextState("END"),
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),
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),
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)
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if wires == 3 or wires == 4:
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fsm.act("END",
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miso_en.eq(1),
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)
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elif wires == 2:
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fsm.act("END",
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miso_en.eq(0),
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NextValue(sync_byte, 0),
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NextState("IDLE")
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)
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else:
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raise ValueError("invalid `wires` count: {}".format(wires))
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