build/altera/quartus.py: added support for ips other than QSYS_FILE
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@ -152,7 +152,8 @@ class AlteraQuartusToolchain(GenericToolchain):
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# Add IPs
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for filename in self.platform.ips:
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qsf.append("set_global_assignment -name QSYS_FILE " + filename.replace("\\", "/"))
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file_ext = os.path.splitext(filename)[1][1:].upper()
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qsf.append(f"set_global_assignment -name {file_ext}_FILE " + filename.replace("\\", "/"))
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# Add include paths
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for path in self.platform.verilog_include_paths:
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