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Move patch script to python-data

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developandplay 2021-06-27 01:31:05 +02:00
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litex/soc/cores/cpu/blackparrot/README.md
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# BlackParrot in LiteX
> **Note:** Tested on Ubuntu 18.04
> **Note:** Since both BlackParrot and Litex are under active development, newer updates on LiteX or BP can cause some compatibility issues. If the most recent BP and LiteX do not work, please use the following link that includes necessary instructions to run BP on Linux with compatible commits.
```
https://github.com/black-parrot/litex/tree/working_linux
```
## Prerequisites and Installing
Please visit https://github.com/scanakci/linux-on-litex-blackparrot for the detailed setup instructions and linux boot-up process.
## Set necessary environment variables for BlackParrot
Running BP in LiteX requires setting some environment variables. Please add the following lines to your bashrc to set them up.
```
pushd .
cd PATH/TO/LITEX/litex/soc/cores/cpu/blackparrot
source ./setEnvironment.sh
popd
```
## Running BIOS
[![asciicast](https://asciinema.org/a/326077.svg)](https://asciinema.org/a/326077)
### Simulation
```
cd $LITEX/litex/tools
./litex_sim.py --cpu-type blackparrot --cpu-variant standard --output-dir build/BP_Trial
```
### FPGA
Generate the bitstream 'top.bit' under build/BP_trial/gateware folder
```
$LITEX/litex/boards/genesys2.py --cpu-type blackparrot --cpu-variant standard --output-dir $PWD/build/BP_Trial --integrated-rom-size 51200 --build
```
In another terminal, launch LiteX terminal.
```
sudo $LITEX/litex/tools/litex_term.py /dev/ttyUSBX
```
Load the FPGA bitstream top.bit to your FPGA (you can use vivado hardware manager)
This step will execute LiteX BIOS.

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litex/soc/cores/cpu/blackparrot/setEnvironment.sh
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#!/bin/bash
## Set common environment variables
export LITEX=$(git rev-parse --show-toplevel)
export BP=$LITEX/../pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog
export BP_LITEX_DIR=$BP/bp_litex
#TODO: check if BP exists and warn user
export BP_COMMON_DIR=$BP/bp_common
export BP_FE_DIR=$BP/bp_fe
export BP_BE_DIR=$BP/bp_be
export BP_ME_DIR=$BP/bp_me
export BP_TOP_DIR=$BP/bp_top
export BP_EXTERNAL_DIR=$BP/external
export BASEJUMP_STL_DIR=$BP_EXTERNAL_DIR/basejump_stl
export LITEX_FPGA_DIR=$BP_LITEX_DIR/fpga
export LITEX_SIMU_DIR=$BP_LITEX_DIR/simulation
##Minor changes in some of the BP files for memory management
sed -i "s/localparam dram_base_addr_gp = 40'h00_8000_0000;/localparam dram_base_addr_gp = 40'h00_7000_0000;/" $BP_COMMON_DIR/src/include/bp_common_pkg.vh
sed -i "s/localparam bp_pc_entry_point_gp=39'h00_8000_0000/localparam bp_pc_entry_point_gp=39'h00_7000_0000/" $BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
sed -i "s/wire local_cmd_li = (cmd_fifo_selected_lo.header.addr < dram_base_addr_gp);/wire local_cmd_li = (cmd_fifo_selected_lo.header.addr < 32'h5000_0000);/" $BP_TOP_DIR/src/v/bp_softcore.v