build/xilinx/vivado: move build_script generation
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@ -298,13 +298,11 @@ class XilinxVivadoToolchain:
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# Generate design constraints (.xdc)
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# Generate design constraints (.xdc)
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tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
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tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
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# Generate build script
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script = _build_script(build_name, toolchain_path, source)
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# Run
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# Run
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if run:
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if run:
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if synth_mode == "yosys":
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if synth_mode == "yosys":
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common._run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
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common._run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
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script = _build_script(build_name, toolchain_path, source)
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_run_script(script)
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_run_script(script)
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os.chdir(cwd)
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os.chdir(cwd)
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