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cpu/microwatt/add_sources: add use_ghdl_yosys_synth parameter to convert microwatt to verilog using GHDL-Yosys-plugin and use converted verilog for build.

This commit is contained in:
Florent Kermarrec 2020-05-18 17:28:41 +02:00
parent b5352f403c
commit a02077d547
1 changed files with 24 additions and 5 deletions
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29
litex/soc/cores/cpu/microwatt/core.py
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@ -39,6 +39,7 @@ class Microwatt(CPU):
flags += "-mno-altivec " flags += "-mno-altivec "
flags += "-mlittle-endian " flags += "-mlittle-endian "
flags += "-mstrict-align " flags += "-mstrict-align "
flags += "-fno-stack-protector "
flags += "-D__microwatt__ " flags += "-D__microwatt__ "
return flags return flags
@ -101,9 +102,8 @@ class Microwatt(CPU):
assert reset_address == 0x00000000 assert reset_address == 0x00000000
@staticmethod @staticmethod
def add_sources(platform): def add_sources(platform, use_ghdl_yosys_plugin=False):
sdir = get_data_mod("cpu", "microwatt").data_location sources = [
platform.add_sources(sdir,
# Common / Types / Helpers # Common / Types / Helpers
"decode_types.vhdl", "decode_types.vhdl",
"wishbone_types.vhdl", "wishbone_types.vhdl",
@ -154,8 +154,27 @@ class Microwatt(CPU):
# Core # Core
"core_debug.vhdl", "core_debug.vhdl",
"core.vhdl", "core.vhdl",
) ]
platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl")) sdir = get_data_mod("cpu", "microwatt").data_location
cdir = os.path.dirname(__file__)
if use_ghdl_yosys_plugin:
from litex.build import tools
import subprocess
ys = []
ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
for source in sources:
ys.append(os.path.join(sdir, source) + " \\")
ys.append(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl") + " \\")
ys.append("-e microwatt_wrapper")
ys.append("chformal -assert -remove")
ys.append("write_verilog {}".format(os.path.join(cdir, "microwatt.v")))
tools.write_to_file(os.path.join(cdir, "microwatt.ys"), "\n".join(ys))
if subprocess.call(["yosys", "-q", "-m", "ghdl", os.path.join(cdir, "microwatt.ys")]):
raise OSError("Unable to convert Microwatt CPU to verilog, please check your GHDL-Yosys-plugin install")
platform.add_source(os.path.join(cdir, "microwatt.v"))
else:
platform.add_sources(sdir, *sources)
platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl"))
def do_finalize(self): def do_finalize(self):
self.specials += Instance("microwatt_wrapper", **self.cpu_params) self.specials += Instance("microwatt_wrapper", **self.cpu_params)