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soc_core: additional CSR safety assertions 

Since csr_data_width=64 has probably never worked properly, remove
it as one of the possible options (to be fixed and re-added later).
Add csr_data_width=16, which has been tested and does work.

Additionally, ensure csr_data_width <= csr_alignment (we should not
attempt to create (sub)registers larger than the CPU's native word
size or XLen).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
This commit is contained in:
Gabriel Somlo 2019-12-12 09:02:47 -05:00
parent fb6b0786b6
commit a0dad1b071
1 changed files with 2 additions and 1 deletions
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3
litex/soc/integration/soc_core.py
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@ -137,7 +137,7 @@ class SoCCore(Module):
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64]
assert csr_data_width in [8, 16, 32]
self.csr_data_width = csr_data_width
self.csr_address_width = csr_address_width
@ -257,6 +257,7 @@ class SoCCore(Module):
csr_alignment = max(csr_alignment, self.cpu.data_width)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment
assert csr_data_width <= csr_alignment
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
if with_wishbone: