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cpu/vexriscv_smp: fix args_read.

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This commit is contained in:
Florent Kermarrec 2020-08-05 17:59:30 +02:00
parent 896b68cd6b
commit a1644510bf
1 changed files with 7 additions and 7 deletions
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14
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -56,7 +56,7 @@ class VexRiscvSMP(CPU):
@staticmethod
def args_read(args):
VexRiscvSMP.cpu_count = args.cpu_count
if args.cpu_count != 1:
if int(args.cpu_count) != 1:
VexRiscvSMP.icache_width = 64
VexRiscvSMP.dcache_width = 64
VexRiscvSMP.dcache_size = 8192
@ -64,12 +64,12 @@ class VexRiscvSMP(CPU):
VexRiscvSMP.dcache_ways = 2
VexRiscvSMP.icache_ways = 2
VexRiscvSMP.coherent_dma = True
if(args.dcache_width): VexRiscvSMP.dcache_width = args.dcache_width
if(args.icache_width): VexRiscvSMP.icache_width = args.icache_width
if(args.icache_width): VexRiscvSMP.dcache_size = args.dcache_size
if(args.icache_width): VexRiscvSMP.icache_size = args.icache_size
if(args.icache_width): VexRiscvSMP.dcache_ways = args.dcache_ways
if(args.icache_width): VexRiscvSMP.icache_ways = args.icache_ways
if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width)
if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width)
if(args.icache_width): VexRiscvSMP.dcache_size = int(args.dcache_size)
if(args.icache_width): VexRiscvSMP.icache_size = int(args.icache_size)
if(args.icache_width): VexRiscvSMP.dcache_ways = int(args.dcache_ways)
if(args.icache_width): VexRiscvSMP.icache_ways = int(args.icache_ways)
@property
def mem_map(self):