Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

fhdl/verilog: properly connect instance inouts

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2012-02-17 11:08:41 +01:00
parent ca7056b07f
commit a1ad30faab
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
migen/fhdl/verilog.py
View file

@ -198,7 +198,7 @@ def _printinstances(f, ns, clk, rst):
r += ns.get_name(x) r += ns.get_name(x)
if x.parameters: r += " " if x.parameters: r += " "
r += "(\n" r += "(\n"
ports = list(x.ins.items()) + list(x.outs.items()) ports = list(x.ins.items()) + list(x.outs.items()) + list(x.inouts.items())
if x.clkport: if x.clkport:
ports.append((x.clkport, clk)) ports.append((x.clkport, clk))
if x.rstport: if x.rstport: