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fhdl/verilog: properly connect instance inouts

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This commit is contained in:
Sebastien Bourdeauducq 2012-02-17 11:08:41 +01:00
parent ca7056b07f
commit a1ad30faab
1 changed files with 1 additions and 1 deletions
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2
migen/fhdl/verilog.py
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@ -198,7 +198,7 @@ def _printinstances(f, ns, clk, rst):
r += ns.get_name(x)
if x.parameters: r += " "
r += "(\n"
ports = list(x.ins.items()) + list(x.outs.items())
ports = list(x.ins.items()) + list(x.outs.items()) + list(x.inouts.items())
if x.clkport:
ports.append((x.clkport, clk))
if x.rstport: