Use automatic register naming
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@ -9,12 +9,10 @@ class ASMIprobe(Module):
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assert(trace_depth < 256)
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assert(trace_depth < 256)
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assert(slot_count < 256)
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assert(slot_count < 256)
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self._slot_count = RegisterField("slot_count", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._slot_count = RegisterField(8, READ_ONLY, WRITE_ONLY)
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self._trace_depth = RegisterField("trace_depth", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._trace_depth = RegisterField(8, READ_ONLY, WRITE_ONLY)
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self._slot_status = [RegisterField("slot_status" + str(i), 2, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._slot_status = [RegisterField(2, READ_ONLY, WRITE_ONLY, name="slot_status" + str(i)) for i in range(slot_count)]
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for i in range(slot_count)]
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self._trace = [RegisterField(8, READ_ONLY, WRITE_ONLY, name="trace" + str(i)) for i in range(trace_depth)]
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self._trace = [RegisterField("trace" + str(i), 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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for i in range(trace_depth)]
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###
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###
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@ -5,21 +5,20 @@ from migen.bank.description import *
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class PhaseInjector(Module, AutoReg):
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class PhaseInjector(Module, AutoReg):
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def __init__(self, phase):
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def __init__(self, phase):
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self._cs = Field("cs", 1, WRITE_ONLY, READ_ONLY)
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self._cs = Field(1, WRITE_ONLY, READ_ONLY)
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self._we = Field("we", 1, WRITE_ONLY, READ_ONLY)
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self._we = Field(1, WRITE_ONLY, READ_ONLY)
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self._cas = Field("cas", 1, WRITE_ONLY, READ_ONLY)
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self._cas = Field(1, WRITE_ONLY, READ_ONLY)
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self._ras = Field("ras", 1, WRITE_ONLY, READ_ONLY)
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self._ras = Field(1, WRITE_ONLY, READ_ONLY)
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self._wren = Field("wren", 1, WRITE_ONLY, READ_ONLY)
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self._wren = Field(1, WRITE_ONLY, READ_ONLY)
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self._rden = Field("rden", 1, WRITE_ONLY, READ_ONLY)
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self._rden = Field(1, WRITE_ONLY, READ_ONLY)
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self._command = RegisterFields("command",
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self._command = RegisterFields(self._cs, self._we, self._cas, self._ras, self._wren, self._rden)
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[self._cs, self._we, self._cas, self._ras, self._wren, self._rden])
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self._command_issue = RegisterRaw()
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self._command_issue = RegisterRaw("command_issue")
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self._address = RegisterField("address", len(phase.address))
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self._address = RegisterField(len(phase.address))
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self._baddress = RegisterField("baddress", len(phase.bank))
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self._baddress = RegisterField(len(phase.bank))
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self._wrdata = RegisterField("wrdata", len(phase.wrdata))
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self._wrdata = RegisterField(len(phase.wrdata))
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self._rddata = RegisterField("rddata", len(phase.rddata), READ_ONLY, WRITE_ONLY)
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self._rddata = RegisterField(len(phase.rddata), READ_ONLY, WRITE_ONLY)
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###
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###
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@ -50,9 +49,9 @@ class DFIInjector(Module, AutoReg):
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self.slave = dfi.Interface(a, ba, d, nphases)
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self.slave = dfi.Interface(a, ba, d, nphases)
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self.master = dfi.Interface(a, ba, d, nphases)
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self.master = dfi.Interface(a, ba, d, nphases)
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self._sel = Field("sel")
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self._sel = Field()
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self._cke = Field("cke")
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self._cke = Field()
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self._control = RegisterFields("control", [self._sel, self._cke])
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self._control = RegisterFields(self._sel, self._cke)
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for n, phase in enumerate(inti.phases):
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for n, phase in enumerate(inti.phases):
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setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
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setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
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@ -6,7 +6,6 @@ from migen.flow.network import *
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from migen.flow.transactions import *
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from migen.flow.transactions import *
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from migen.flow import plumbing
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from migen.flow import plumbing
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from migen.actorlib import misc, dma_asmi, structuring, sim, spi
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from migen.actorlib import misc, dma_asmi, structuring, sim, spi
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from migen.bank.description import *
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_hbits = 11
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_hbits = 11
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_vbits = 11
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_vbits = 11
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@ -17,9 +17,9 @@ def encode_version(version):
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class Identifier(Module, AutoReg):
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class Identifier(Module, AutoReg):
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def __init__(self, sysid, version, frequency):
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def __init__(self, sysid, version, frequency):
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self._r_sysid = RegisterField("sysid", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._r_sysid = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._r_version = RegisterField("version", 16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._r_version = RegisterField(16, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._r_frequency = RegisterField("frequency", 32, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._r_frequency = RegisterField(32, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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###
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###
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@ -23,11 +23,11 @@ class MiniMAC(Module, AutoReg):
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self.phy_rst_n = Signal()
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self.phy_rst_n = Signal()
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# CPU interface
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# CPU interface
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self._phy_reset = RegisterField("phy_reset", reset=1)
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self._phy_reset = RegisterField(reset=1)
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self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._rx_count_0 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._rx_count_1 = RegisterField(_count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE)
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self._tx_count = RegisterField(_count_width, access_dev=READ_WRITE)
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self._tx_start = RegisterRaw("tx_start")
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self._tx_start = RegisterRaw()
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self.submodules.ev = EventManager()
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self.submodules.ev = EventManager()
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self.ev.rx0 = EventSourcePulse()
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self.ev.rx0 = EventSourcePulse()
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@ -5,9 +5,9 @@ from migen.bank.eventmanager import *
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class Timer(Module, AutoReg):
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class Timer(Module, AutoReg):
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def __init__(self, width=32):
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def __init__(self, width=32):
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self._en = RegisterField("en")
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self._en = RegisterField()
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self._value = RegisterField("value", width, access_dev=READ_WRITE)
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self._value = RegisterField(width, access_dev=READ_WRITE)
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self._reload = RegisterField("reload", width)
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self._reload = RegisterField(width)
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self.submodules.ev = EventManager()
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self.submodules.ev = EventManager()
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self.ev.zero = EventSourceLevel()
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self.ev.zero = EventSourceLevel()
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@ -6,8 +6,8 @@ from migen.bank.eventmanager import *
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class UART(Module, AutoReg):
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class UART(Module, AutoReg):
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def __init__(self, clk_freq, baud=115200):
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def __init__(self, clk_freq, baud=115200):
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self._rxtx = RegisterRaw("rxtx", 8)
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self._rxtx = RegisterRaw(8)
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self._divisor = RegisterField("divisor", 16, reset=int(clk_freq/baud/16))
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self._divisor = RegisterField(16, reset=int(clk_freq/baud/16))
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self.submodules.ev = EventManager()
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self.submodules.ev = EventManager()
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self.ev.tx = EventSourceLevel()
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self.ev.tx = EventSourceLevel()
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