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targets/xilinx: remove keep attribute on clock going to idelayctrl 

Causes P&R issues with Vivado.
This commit is contained in:
Florent Kermarrec 2019-04-23 10:51:36 +02:00
parent ea8dbff86e
commit a24bf72fc7
6 changed files with 0 additions and 12 deletions
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1
litex/boards/targets/arty.py
View File

@ -31,7 +31,6 @@ class _CRG(Module):
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.cd_clk200.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))

1
litex/boards/targets/genesys2.py
View File

@ -29,7 +29,6 @@ class _CRG(Module):
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_clk200.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))

1
litex/boards/targets/kc705.py
View File

@ -29,7 +29,6 @@ class _CRG(Module):
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_clk200.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(platform.request("cpu_reset"))

2
litex/boards/targets/kcu105.py
View File

@ -30,8 +30,6 @@ class _CRG(Module):
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_clk200.clk.attr.add("keep")
self.cd_ic.clk.attr.add("keep")
self.submodules.pll = pll = USMMCM(speedgrade=-2)
self.comb += pll.reset.eq(platform.request("cpu_reset"))

4
litex/boards/targets/nexys4ddr.py
View File

@ -23,15 +23,12 @@ class _CRG(Module):
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys2x.clk.attr.add("keep")
self.cd_sys2x_dqs.clk.attr.add("keep")
self.cd_clk200.clk.attr.add("keep")
self.cd_clk100.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
@ -40,7 +37,6 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)

3
litex/boards/targets/nexys_video.py
View File

@ -32,8 +32,6 @@ class _CRG(Module):
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.cd_clk200.clk.attr.add("keep")
self.cd_clk100.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
@ -42,7 +40,6 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)