utils: add litex_read_verilog utility

generate Migen's modules from verilog files
This commit is contained in:
Florent Kermarrec 2018-11-16 16:03:23 +01:00
parent a538d36268
commit a25645afa6
2 changed files with 61 additions and 0 deletions

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@ -0,0 +1,60 @@
#!/usr/bin/env python3
import os
import sys
import json
from litex.build import tools
def main():
if len(sys.argv) < 2:
print("usage: litex_read_verilog verilog_file [module]")
exit(1)
verilog_file = sys.argv[1]
json_file = verilog_file + ".json"
module = None if len(sys.argv) < 3 else sys.argv[2]
# use yosys to convert verilog to json
yosys_v2j = "\n".join([
"read_verilog -sv {}".format(verilog_file),
"write_json {}.json".format(verilog_file)
])
tools.write_to_file("yosys_v2j.ys", yosys_v2j)
os.system("yosys -q yosys_v2j.ys")
# load json and convert to migen module
f = open(json_file, "r")
j = json.load(f)
# create list of modules
modules = [module] if module is not None else j["modules"].keys()
# create migen definitions
for module in modules:
migen_def = []
migen_def.append("class {}(Module):".format(module))
migen_def.append(" "*4 + "def __init__(self):")
for name, info in j["modules"][module]["ports"].items():
length = "" if len(info["bits"]) == 1 else len(info["bits"])
migen_def.append(" " * 8 + "self.{} = Signal({})".format(name, length))
migen_def.append("")
migen_def.append(" "*4 + "# # #")
migen_def.append("")
migen_def.append(" "*4 + "self.specials += Instance(\"{}\",".format(module))
for name, info in j["modules"][module]["ports"].items():
io_prefix = {
"input": "i",
"output": "o",
"inout": "io"
}[info["direction"]]
migen_def.append(" "*8 + "{}_{}=self.{},".format(io_prefix, name, name))
migen_def.append(" "*4 + ")")
migen_def.append("")
print("\n".join(migen_def))
# keep things clean after us
os.system("rm " + json_file)
if __name__ == "__main__":
main()

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@ -40,6 +40,7 @@ setup(
"litex_term=litex.utils.litex_term:main", "litex_term=litex.utils.litex_term:main",
"litex_server=litex.utils.litex_server:main", "litex_server=litex.utils.litex_server:main",
"litex_sim=litex.utils.litex_sim:main", "litex_sim=litex.utils.litex_sim:main",
"litex_read_verilog=litex.utils.litex_read_verilog:main",
"litex_simple=litex.boards.targets.simple:main", "litex_simple=litex.boards.targets.simple:main",
], ],
}, },