utils: add litex_read_verilog utility
generate Migen's modules from verilog files
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#!/usr/bin/env python3
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import os
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import sys
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import json
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from litex.build import tools
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def main():
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if len(sys.argv) < 2:
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print("usage: litex_read_verilog verilog_file [module]")
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exit(1)
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verilog_file = sys.argv[1]
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json_file = verilog_file + ".json"
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module = None if len(sys.argv) < 3 else sys.argv[2]
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# use yosys to convert verilog to json
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yosys_v2j = "\n".join([
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"read_verilog -sv {}".format(verilog_file),
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"write_json {}.json".format(verilog_file)
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])
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tools.write_to_file("yosys_v2j.ys", yosys_v2j)
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os.system("yosys -q yosys_v2j.ys")
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# load json and convert to migen module
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f = open(json_file, "r")
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j = json.load(f)
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# create list of modules
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modules = [module] if module is not None else j["modules"].keys()
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# create migen definitions
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for module in modules:
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migen_def = []
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migen_def.append("class {}(Module):".format(module))
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migen_def.append(" "*4 + "def __init__(self):")
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for name, info in j["modules"][module]["ports"].items():
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length = "" if len(info["bits"]) == 1 else len(info["bits"])
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migen_def.append(" " * 8 + "self.{} = Signal({})".format(name, length))
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migen_def.append("")
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migen_def.append(" "*4 + "# # #")
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migen_def.append("")
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migen_def.append(" "*4 + "self.specials += Instance(\"{}\",".format(module))
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for name, info in j["modules"][module]["ports"].items():
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io_prefix = {
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"input": "i",
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"output": "o",
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"inout": "io"
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}[info["direction"]]
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migen_def.append(" "*8 + "{}_{}=self.{},".format(io_prefix, name, name))
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migen_def.append(" "*4 + ")")
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migen_def.append("")
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print("\n".join(migen_def))
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# keep things clean after us
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os.system("rm " + json_file)
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if __name__ == "__main__":
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main()
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