LiteXXX cores: fix frequency print in test/test_regs.py
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d2cb41bc63
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@ -4,7 +4,7 @@ def main(wb):
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###
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###
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print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
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print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
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print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
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print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
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print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
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print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
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SRAM_BASE = 0x02000000
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SRAM_BASE = 0x02000000
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wb.write(SRAM_BASE, [i for i in range(64)])
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wb.write(SRAM_BASE, [i for i in range(64)])
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print(wb.read(SRAM_BASE, 64))
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print(wb.read(SRAM_BASE, 64))
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@ -4,6 +4,6 @@ def main(wb):
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###
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###
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print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
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print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
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print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
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print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
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print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
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print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
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###
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###
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wb.close()
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wb.close()
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@ -4,6 +4,6 @@ def main(wb):
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###
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###
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print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
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print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
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print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
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print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
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print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
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print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
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###
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###
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wb.close()
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wb.close()
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