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LiteXXX cores: fix frequency print in test/test_regs.py

This commit is contained in:
Florent Kermarrec 2015-03-17 16:01:12 +01:00
parent d2cb41bc63
commit a266deb58e
3 changed files with 3 additions and 3 deletions
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2
misoclib/com/liteeth/example_designs/test/test_regs.py
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@ -4,7 +4,7 @@ def main(wb):
###
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))

2
misoclib/mem/litesata/example_designs/test/test_regs.py
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@ -4,6 +4,6 @@ def main(wb):
###
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
###
wb.close()

2
misoclib/tools/litescope/example_designs/test/test_regs.py
View File

@ -4,6 +4,6 @@ def main(wb):
###
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
###
wb.close()