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interconnect/packet: Switch to LiteXModule.

This commit is contained in:
Florent Kermarrec 2023-10-27 11:07:31 +02:00
parent fa521f5c89
commit a2820cba96
1 changed files with 11 additions and 13 deletions
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24
litex/soc/interconnect/packet.py
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@ -9,8 +9,6 @@ from math import log2
from migen import * from migen import *
from migen.genlib.roundrobin import * from migen.genlib.roundrobin import *
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
from litex.gen import * from litex.gen import *
@ -18,7 +16,7 @@ from litex.soc.interconnect import stream
# Status ------------------------------------------------------------------------------------------- # Status -------------------------------------------------------------------------------------------
class Status(Module): class Status(LiteXModule):
def __init__(self, endpoint): def __init__(self, endpoint):
self.first = Signal(reset=1) self.first = Signal(reset=1)
self.last = Signal() self.last = Signal()
@ -38,7 +36,7 @@ class Status(Module):
# Arbiter ------------------------------------------------------------------------------------------ # Arbiter ------------------------------------------------------------------------------------------
class Arbiter(Module): class Arbiter(LiteXModule):
def __init__(self, masters, slave): def __init__(self, masters, slave):
if len(masters) == 0: if len(masters) == 0:
pass pass
@ -46,7 +44,7 @@ class Arbiter(Module):
self.grant = Signal() self.grant = Signal()
self.comb += masters.pop().connect(slave) self.comb += masters.pop().connect(slave)
else: else:
self.submodules.rr = RoundRobin(len(masters)) self.rr = RoundRobin(len(masters))
self.grant = self.rr.grant self.grant = self.rr.grant
cases = {} cases = {}
for i, master in enumerate(masters): for i, master in enumerate(masters):
@ -58,7 +56,7 @@ class Arbiter(Module):
# Dispatcher --------------------------------------------------------------------------------------- # Dispatcher ---------------------------------------------------------------------------------------
class Dispatcher(Module): class Dispatcher(LiteXModule):
def __init__(self, master, slaves, one_hot=False): def __init__(self, master, slaves, one_hot=False):
if len(slaves) == 0: if len(slaves) == 0:
self.sel = Signal() self.sel = Signal()
@ -157,7 +155,7 @@ class Header:
# Packetizer --------------------------------------------------------------------------------------- # Packetizer ---------------------------------------------------------------------------------------
class Packetizer(Module): class Packetizer(LiteXModule):
def __init__(self, sink_description, source_description, header): def __init__(self, sink_description, source_description, header):
self.sink = sink = stream.Endpoint(sink_description) self.sink = sink = stream.Endpoint(sink_description)
self.source = source = stream.Endpoint(source_description) self.source = source = stream.Endpoint(source_description)
@ -186,7 +184,7 @@ class Packetizer(Module):
self.sync += If(sr_shift, sr.eq(sr[data_width:])) self.sync += If(sr_shift, sr.eq(sr[data_width:]))
# FSM. # FSM.
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm_from_idle = Signal() fsm_from_idle = Signal()
fsm.act("IDLE", fsm.act("IDLE",
sink.ready.eq(1), sink.ready.eq(1),
@ -260,7 +258,7 @@ class Packetizer(Module):
# Depacketizer ------------------------------------------------------------------------------------- # Depacketizer -------------------------------------------------------------------------------------
class Depacketizer(Module): class Depacketizer(LiteXModule):
def __init__(self, sink_description, source_description, header): def __init__(self, sink_description, source_description, header):
self.sink = sink = stream.Endpoint(sink_description) self.sink = sink = stream.Endpoint(sink_description)
self.source = source = stream.Endpoint(source_description) self.source = source = stream.Endpoint(source_description)
@ -294,7 +292,7 @@ class Depacketizer(Module):
self.comb += header.decode(self.header, source) self.comb += header.decode(self.header, source)
# FSM. # FSM.
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.fsm = fsm = FSM(reset_state="IDLE")
fsm_from_idle = Signal() fsm_from_idle = Signal()
fsm.act("IDLE", fsm.act("IDLE",
sink.ready.eq(1), sink.ready.eq(1),
@ -361,7 +359,7 @@ class Depacketizer(Module):
# PacketFIFO --------------------------------------------------------------------------------------- # PacketFIFO ---------------------------------------------------------------------------------------
class PacketFIFO(Module): class PacketFIFO(LiteXModule):
def __init__(self, layout, payload_depth, param_depth=None, buffered=False): def __init__(self, layout, payload_depth, param_depth=None, buffered=False):
self.sink = sink = stream.Endpoint(layout) self.sink = sink = stream.Endpoint(layout)
self.source = source = stream.Endpoint(layout) self.source = source = stream.Endpoint(layout)
@ -380,8 +378,8 @@ class PacketFIFO(Module):
payload_description = stream.EndpointDescription(payload_layout=payload_layout) payload_description = stream.EndpointDescription(payload_layout=payload_layout)
param_description = stream.EndpointDescription(param_layout=param_layout) param_description = stream.EndpointDescription(param_layout=param_layout)
param_depth = param_depth + 1 # +1 to allow dequeuing current while enqueuing next. param_depth = param_depth + 1 # +1 to allow dequeuing current while enqueuing next.
self.submodules.payload_fifo = payload_fifo = stream.SyncFIFO(payload_description, payload_depth, buffered) self.payload_fifo = payload_fifo = stream.SyncFIFO(payload_description, payload_depth, buffered)
self.submodules.param_fifo = param_fifo = stream.SyncFIFO(param_description, param_depth, buffered) self.param_fifo = param_fifo = stream.SyncFIFO(param_description, param_depth, buffered)
# Connect Sink to FIFOs. # Connect Sink to FIFOs.
self.comb += [ self.comb += [