build/xilinx/vivado: Switch from .format to f-strings.
This commit is contained in:
Florent Kermarrec
parent
2fba07daf8
commit
a286d77e01
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@ -37,7 +37,7 @@ def _format_xdc_constraint(c):
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elif isinstance(c, Inverted):
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return None
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else:
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raise ValueError("unknown constraint {}".format(c))
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raise ValueError(f"unknown constraint {c}")
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def _format_xdc(signame, resname, *constraints):
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@ -45,7 +45,7 @@ def _format_xdc(signame, resname, *constraints):
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fmt_r = resname[0] + ":" + str(resname[1])
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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r = "# {}\n".format(fmt_r)
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r = f"# {fmt_r}\n"
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for c in fmt_c:
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if c is not None:
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r += c + " [get_ports {" + signame + "}]\n"
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@ -143,7 +143,7 @@ class XilinxVivadoToolchain(GenericToolchain):
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elif isinstance(c, Inverted):
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return None
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else:
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raise ValueError("unknown constraint {}".format(c))
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raise ValueError(f"unknown constraint {c}")
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def build_io_constraints(self):
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r = _build_xdc(self.named_sc, self.named_pc)
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@ -208,7 +208,7 @@ class XilinxVivadoToolchain(GenericToolchain):
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# Create project
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tcl.append("\n# Create Project\n")
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tcl.append("create_project -force -name {} -part {}".format(self._build_name, self.platform.device))
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tcl.append(f"create_project -force -name {self._build_name} -part {self.platform.device}")
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tcl.append("set_msg_config -id {Common 17-55} -new_severity {Warning}")
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# Enable Xilinx Parameterized Macros
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@ -223,15 +223,13 @@ class XilinxVivadoToolchain(GenericToolchain):
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for filename, language, library, *copy in self.platform.sources:
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filename_tcl = "{" + filename + "}"
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if (language == "systemverilog"):
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tcl.append("read_verilog -v " + filename_tcl)
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tcl.append("set_property file_type SystemVerilog [get_files {}]"
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.format(filename_tcl))
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tcl.append(f"read_verilog -v {filename_tcl}")
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tcl.append(f"set_property file_type SystemVerilog [get_files {filename_tcl}]")
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elif (language == "verilog"):
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tcl.append("read_verilog " + filename_tcl)
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tcl.append(f"read_verilog {filename_tcl}")
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elif (language == "vhdl"):
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tcl.append("read_vhdl -vhdl2008 " + filename_tcl)
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tcl.append("set_property library {} [get_files {}]"
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.format(library, filename_tcl))
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tcl.append(f"read_vhdl -vhdl2008 {filename_tcl}")
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tcl.append(f"set_property library {library} [get_files {filename_tcl}]")
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else:
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tcl.append("add_files " + filename_tcl)
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@ -239,7 +237,7 @@ class XilinxVivadoToolchain(GenericToolchain):
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tcl.append("\n# Add EDIFs\n")
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for filename in self.platform.edifs:
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filename_tcl = "{" + filename + "}"
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tcl.append("read_edif " + filename_tcl)
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tcl.append(f"read_edif {filename_tcl}")
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# Add IPs
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tcl.append("\n# Add IPs\n")
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@ -249,18 +247,18 @@ class XilinxVivadoToolchain(GenericToolchain):
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else:
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filename_tcl = "{" + filename + "}"
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ip = os.path.splitext(os.path.basename(filename))[0]
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tcl.append("read_ip " + filename_tcl)
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tcl.append("upgrade_ip [get_ips {}]".format(ip))
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tcl.append("generate_target all [get_ips {}]".format(ip))
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tcl.append("synth_ip [get_ips {}] -force".format(ip))
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tcl.append("get_files -all -of_objects [get_files {}]".format(filename_tcl))
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tcl.append(f"read_ip {filename_tcl}")
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tcl.append(f"upgrade_ip [get_ips {ip}]")
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tcl.append(f"generate_target all [get_ips {ip}]")
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tcl.append(f"synth_ip [get_ips {ip}] -force")
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tcl.append(f"get_files -all -of_objects [get_files {filename_tcl}]")
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if disable_constraints:
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tcl.append("set_property is_enabled false [get_files -of_objects [get_files {}] -filter {{FILE_TYPE== XDC}}]".format(filename_tcl))
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tcl.append(f"set_property is_enabled false [get_files -of_objects [get_files {filename_tcl}] -filter {{FILE_TYPE== XDC}}]")
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# Add constraints
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tcl.append("\n# Add constraints\n")
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tcl.append("read_xdc {}.xdc".format(self._build_name))
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tcl.append("set_property PROCESSING_ORDER EARLY [get_files {}.xdc]".format(self._build_name))
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tcl.append(f"read_xdc {self._build_name}.xdc")
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tcl.append(f"set_property PROCESSING_ORDER EARLY [get_files {self._build_name}.xdc]")
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# Add pre-synthesis commands
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tcl.append("\n# Add pre-synthesis commands\n")
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@ -269,30 +267,29 @@ class XilinxVivadoToolchain(GenericToolchain):
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# Synthesis
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if self._synth_mode == "vivado":
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tcl.append("\n# Synthesis\n")
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synth_cmd = "synth_design -directive {} -top {} -part {}".format(self.vivado_synth_directive,
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self._build_name, self.platform.device)
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synth_cmd = f"synth_design -directive {self.vivado_synth_directive} -top {self._build_name} -part {self.platform.device}"
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if self.platform.verilog_include_paths:
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synth_cmd += " -include_dirs {{{}}}".format(" ".join(self.platform.verilog_include_paths))
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synth_cmd += f" -include_dirs \{{" ".join(self.platform.verilog_include_paths)}\}"
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tcl.append(synth_cmd)
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elif self._synth_mode == "yosys":
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tcl.append("\n# Read Yosys EDIF\n")
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tcl.append("read_edif {}.edif".format(self._build_name))
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tcl.append("link_design -top {} -part {}".format(self._build_name, self.platform.device))
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tcl.append(f"read_edif {self._build_name}.edif")
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tcl.append(f"link_design -top {self._build_name} -part {self.platform.device}")
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else:
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raise OSError("Unknown synthesis mode! {}".format(self._synth_mode))
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raise OSError(f"Unknown synthesis mode! {self._synth_mode}")
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tcl.append("\n# Synthesis report\n")
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tcl.append("report_timing_summary -file {}_timing_synth.rpt".format(self._build_name))
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_synth.rpt".format(self._build_name))
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tcl.append("report_utilization -file {}_utilization_synth.rpt".format(self._build_name))
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tcl.append(f"report_timing_summary -file {self._build_name}_timing_synth.rpt")
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tcl.append(f"report_utilization -hierarchical -file {self._build_name}_utilization_hierarchical_synth.rpt")
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tcl.append(f"report_utilization -file {self._build_name}_utilization_synth.rpt")
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# Optimize
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tcl.append("\n# Optimize design\n")
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tcl.append("opt_design -directive {}".format(self.opt_directive))
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tcl.append(f"opt_design -directive {self.opt_directive}")
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# Incremental implementation
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if self.incremental_implementation:
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tcl.append("\n# Read design checkpoint\n")
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tcl.append("read_checkpoint -incremental {}_route.dcp".format(self._build_name))
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tcl.append(f"read_checkpoint -incremental {self._build_name}_route.dcp")
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# Add pre-placement commands
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tcl.append("\n# Add pre-placement commands\n")
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@ -300,15 +297,15 @@ class XilinxVivadoToolchain(GenericToolchain):
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# Placement
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tcl.append("\n# Placement\n")
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tcl.append("place_design -directive {}".format(self.vivado_place_directive))
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tcl.append(f"place_design -directive {self.vivado_place_directive}")
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if self.vivado_post_place_phys_opt_directive:
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tcl.append("phys_opt_design -directive {}".format(self.vivado_post_place_phys_opt_directive))
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tcl.append(f"phys_opt_design -directive {self.vivado_post_place_phys_opt_directive}")
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tcl.append("\n# Placement report\n")
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tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(self._build_name))
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tcl.append("report_utilization -file {}_utilization_place.rpt".format(self._build_name))
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tcl.append("report_io -file {}_io.rpt".format(self._build_name))
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tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(self._build_name))
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tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(self._build_name))
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tcl.append(f"report_utilization -hierarchical -file {self._build_name}_utilization_hierarchical_place.rpt")
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tcl.append(f"report_utilization -file {self._build_name}_utilization_place.rpt")
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tcl.append(f"report_io -file {self._build_name}_io.rpt")
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tcl.append(f"report_control_sets -verbose -file {self._build_name}_control_sets.rpt")
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tcl.append(f"report_clock_utilization -file {self._build_name}_clock_utilization.rpt")
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# Add pre-routing commands
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tcl.append("\n# Add pre-routing commands\n")
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@ -316,21 +313,21 @@ class XilinxVivadoToolchain(GenericToolchain):
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# Routing
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tcl.append("\n# Routing\n")
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tcl.append("route_design -directive {}".format(self.vivado_route_directive))
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tcl.append("phys_opt_design -directive {}".format(self.vivado_post_route_phys_opt_directive))
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tcl.append("write_checkpoint -force {}_route.dcp".format(self._build_name))
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tcl.append(f"route_design -directive {self.vivado_route_directive}")
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tcl.append(f"phys_opt_design -directive {self.vivado_post_route_phys_opt_directive}")
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tcl.append(f"write_checkpoint -force {self._build_name}_route.dcp")
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tcl.append("\n# Routing report\n")
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tcl.append("report_timing_summary -no_header -no_detailed_paths")
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tcl.append("report_route_status -file {}_route_status.rpt".format(self._build_name))
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tcl.append("report_drc -file {}_drc.rpt".format(self._build_name))
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tcl.append("report_timing_summary -datasheet -max_paths 10 -file {}_timing.rpt".format(self._build_name))
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tcl.append("report_power -file {}_power.rpt".format(self._build_name))
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tcl.append(f"report_route_status -file {self._build_name}_route_status.rpt")
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tcl.append(f"report_drc -file {self._build_name}_drc.rpt")
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tcl.append(f"report_timing_summary -datasheet -max_paths 10 -file {self._build_name}_timing.rpt")
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tcl.append(f"report_power -file {self._build_name}_power.rpt")
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for bitstream_command in self.bitstream_commands:
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tcl.append(bitstream_command.format(build_name=self._build_name))
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# Bitstream generation
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tcl.append("\n# Bitstream generation\n")
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tcl.append("write_bitstream -force {}.bit ".format(self._build_name))
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tcl.append(f"write_bitstream -force {self._build_name}.bit ")
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for additional_command in self.additional_commands:
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tcl.append(additional_command.format(build_name=self._build_name))
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@ -353,7 +350,7 @@ class XilinxVivadoToolchain(GenericToolchain):
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#script_contents += common._build_yosys_project(platform=self.platform, build_name=self._build_name) # FIXME.
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script_contents += "vivado -mode batch -source " + self._build_name + ".tcl\n"
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script_file = "build_" + self._build_name + "." + script_ext
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script_file = "build_" + self._build_name + "." + script_ext
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tools.write_to_file(script_file, script_contents)
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return script_file
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