soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic"
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Florent Kermarrec
parent
19d3acfc71
commit
a2938a7ae7
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@ -1,128 +0,0 @@
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# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
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# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
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# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
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# License: BSD
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from migen import *
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from migen.genlib.record import Record
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr_eventmanager import *
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class JTAG_atlantic(Module):
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def __init__(self,
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tx_fifo_depth=32,
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rx_fifo_depth=32):
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# todo fifo depth calculation?
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self.tx_valid = Signal()
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self.tx_ready = Signal()
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self.tx_data = Signal(8)
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self.rx_valid = Signal()
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self.rx_ready = Signal()
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self.rx_pause = Signal()
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self.rx_data = Signal(8)
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self.specials += Instance("alt_jtag_atlantic",
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#p_INSTANCE_ID = 0, # should be 0, can not be "0" or 1'b0 !
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p_LOG2_RXFIFO_DEPTH = "5", # should be INTEGR, but not recognized by migen?
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p_LOG2_TXFIFO_DEPTH = "5", # "<>" is OK, can not be left out
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p_SLD_AUTO_INSTANCE_INDEX = "YES",
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i_clk = ClockSignal("sys"),
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i_rst_n = ~ResetSignal("sys"),
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# we transmit here - our tx
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i_r_dat = self.tx_data,
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i_r_val = self.tx_valid,
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o_r_ena = self.tx_ready,
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# transmit part of uart - our RX
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o_t_dat = self.rx_data,
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i_t_dav = self.rx_ready,
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o_t_ena = self.rx_valid,
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o_t_pause = self.rx_pause
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)
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# Altera Atlantic JTAG UART ----------------------------------------------------------------------------------------
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class UART_atlantic(Module, AutoCSR):
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def __init__(self, platform,
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tx_fifo_depth=32,
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rx_fifo_depth=32):
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self._rxtx = CSR(8)
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self._txfull = CSRStatus()
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self._rxempty = CSRStatus()
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self.submodules.ev = EventManager()
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self.ev.tx = EventSourceProcess()
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self.ev.rx = EventSourceProcess()
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self.ev.finalize()
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#
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self.submodules.jtag = JTAG_atlantic(tx_fifo_depth, rx_fifo_depth)
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# TX is working, can be simplified maybe?
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tx_data = Signal(8)
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tx_valid = Signal()
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tx_pending = Signal()
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tx_busy = Signal()
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self.sync += [
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If(self._rxtx.re,
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tx_data.eq(self._rxtx.r), # latch tx data
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tx_pending.eq(1), #
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tx_busy.eq(1), #
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),
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If(tx_pending & self.jtag.tx_ready,
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tx_valid.eq(1), #
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tx_pending.eq(0)
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),
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If(tx_valid & ~self.jtag.tx_ready,
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tx_valid.eq(0), # clear valid
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tx_busy.eq(0), #
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),
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]
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self.comb += [
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self.jtag.tx_valid.eq(tx_valid),
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self.jtag.tx_data.eq(tx_data),
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self._txfull.status.eq(~self.jtag.tx_ready | tx_busy),
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# Generate TX IRQ when tx_fifo becomes non-full
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self.ev.tx.trigger.eq(~self.jtag.tx_ready | tx_busy)
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]
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# RX
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rx_data = Signal(8)
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rx_ready = Signal(reset=1)
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rx_pending = Signal(reset=0)
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self.sync += [
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If(self.jtag.rx_valid & rx_ready,
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rx_data.eq(self.jtag.rx_data),
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rx_pending.eq(1),
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rx_ready.eq(0)
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),
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If(self.ev.rx.clear,
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rx_pending.eq(0),
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rx_ready.eq(1),
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),
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]
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self.comb += [
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self._rxempty.status.eq(~rx_pending),
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self._rxtx.w.eq(rx_data),
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self.jtag.rx_ready.eq(rx_ready),
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# Generate RX IRQ when rx_fifo becomes non-empty
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self.ev.rx.trigger.eq(~rx_pending)
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]
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#
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# todo atlantic wishbone bridge?
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#
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@ -0,0 +1,34 @@
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# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>$
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from litex.soc.interconnect import stream
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# Altera Atlantic JTAG -----------------------------------------------------------------------------
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class JTAGAtlantic(Module):
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def __init__(self):
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self.sink = sink = stream.Endpoint([("data", 8)])
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self.source = source = stream.Endpoint([("data", 8)])
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# # #
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self.specials += Instance("alt_jtag_atlantic",
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# Parameters
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p_LOG2_RXFIFO_DEPTH="5", # FIXME: expose?
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p_LOG2_TXFIFO_DEPTH="5", # FIXME: expose?
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p_SLD_AUTO_INSTANCE_INDEX="YES",
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# Clk/Rst
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i_clk=ClockSignal("sys"),
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i_rst_n=~ResetSignal("sys"),
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# TX
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i_r_dat=sink.data,
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i_r_val=sink.valid,
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o_r_ena=sink.ready,
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# RX
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o_t_dat=source.data,
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i_t_dav=source.ready,
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o_t_ena=source.valid,
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)
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@ -315,7 +315,11 @@ class SoCCore(Module):
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if uart_stub:
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self.submodules.uart = uart.UARTStub()
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else:
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self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
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if uart_name == "jtag_atlantic":
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from litex.soc.cores.jtag import JTAGAtlantic
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self.submodules.uart_phy = JTAGAtlantic()
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else:
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self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
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self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
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self.add_csr("uart_phy", allow_user_defined=True)
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self.add_csr("uart", allow_user_defined=True)
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