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soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic"

This commit is contained in:
Florent Kermarrec 2019-08-31 18:32:35 +02:00
parent 19d3acfc71
commit a2938a7ae7
3 changed files with 39 additions and 129 deletions
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128
litex/soc/cores/atlantic.py
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@ -1,128 +0,0 @@
# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>
# This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
# This file is Copyright (c) 2018 Tim 'mithro' Ansell <me@mith.ro>
# License: BSD
from migen import *
from migen.genlib.record import Record
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
class JTAG_atlantic(Module):
def __init__(self,
tx_fifo_depth=32,
rx_fifo_depth=32):
# todo fifo depth calculation?
self.tx_valid = Signal()
self.tx_ready = Signal()
self.tx_data = Signal(8)
self.rx_valid = Signal()
self.rx_ready = Signal()
self.rx_pause = Signal()
self.rx_data = Signal(8)
self.specials += Instance("alt_jtag_atlantic",
#p_INSTANCE_ID = 0, # should be 0, can not be "0" or 1'b0 !
p_LOG2_RXFIFO_DEPTH = "5", # should be INTEGR, but not recognized by migen?
p_LOG2_TXFIFO_DEPTH = "5", # "<>" is OK, can not be left out
p_SLD_AUTO_INSTANCE_INDEX = "YES",
i_clk = ClockSignal("sys"),
i_rst_n = ~ResetSignal("sys"),
# we transmit here - our tx
i_r_dat = self.tx_data,
i_r_val = self.tx_valid,
o_r_ena = self.tx_ready,
# transmit part of uart - our RX
o_t_dat = self.rx_data,
i_t_dav = self.rx_ready,
o_t_ena = self.rx_valid,
o_t_pause = self.rx_pause
)
# Altera Atlantic JTAG UART ----------------------------------------------------------------------------------------
class UART_atlantic(Module, AutoCSR):
def __init__(self, platform,
tx_fifo_depth=32,
rx_fifo_depth=32):
self._rxtx = CSR(8)
self._txfull = CSRStatus()
self._rxempty = CSRStatus()
self.submodules.ev = EventManager()
self.ev.tx = EventSourceProcess()
self.ev.rx = EventSourceProcess()
self.ev.finalize()
#
self.submodules.jtag = JTAG_atlantic(tx_fifo_depth, rx_fifo_depth)
# TX is working, can be simplified maybe?
tx_data = Signal(8)
tx_valid = Signal()
tx_pending = Signal()
tx_busy = Signal()
self.sync += [
If(self._rxtx.re,
tx_data.eq(self._rxtx.r), # latch tx data
tx_pending.eq(1), #
tx_busy.eq(1), #
),
If(tx_pending & self.jtag.tx_ready,
tx_valid.eq(1), #
tx_pending.eq(0)
),
If(tx_valid & ~self.jtag.tx_ready,
tx_valid.eq(0), # clear valid
tx_busy.eq(0), #
),
]
self.comb += [
self.jtag.tx_valid.eq(tx_valid),
self.jtag.tx_data.eq(tx_data),
self._txfull.status.eq(~self.jtag.tx_ready | tx_busy),
# Generate TX IRQ when tx_fifo becomes non-full
self.ev.tx.trigger.eq(~self.jtag.tx_ready | tx_busy)
]
# RX
rx_data = Signal(8)
rx_ready = Signal(reset=1)
rx_pending = Signal(reset=0)
self.sync += [
If(self.jtag.rx_valid & rx_ready,
rx_data.eq(self.jtag.rx_data),
rx_pending.eq(1),
rx_ready.eq(0)
),
If(self.ev.rx.clear,
rx_pending.eq(0),
rx_ready.eq(1),
),
]
self.comb += [
self._rxempty.status.eq(~rx_pending),
self._rxtx.w.eq(rx_data),
self.jtag.rx_ready.eq(rx_ready),
# Generate RX IRQ when rx_fifo becomes non-empty
self.ev.rx.trigger.eq(~rx_pending)
]
#
# todo atlantic wishbone bridge?
#

34
litex/soc/cores/jtag.py Normal file
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@ -0,0 +1,34 @@
# This file is Copyright (c) 2019 Antti Lukats <antti.lukats@gmail.com>$
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
from migen import *
from litex.soc.interconnect import stream
# Altera Atlantic JTAG -----------------------------------------------------------------------------
class JTAGAtlantic(Module):
def __init__(self):
self.sink = sink = stream.Endpoint([("data", 8)])
self.source = source = stream.Endpoint([("data", 8)])
# # #
self.specials += Instance("alt_jtag_atlantic",
# Parameters
p_LOG2_RXFIFO_DEPTH="5", # FIXME: expose?
p_LOG2_TXFIFO_DEPTH="5", # FIXME: expose?
p_SLD_AUTO_INSTANCE_INDEX="YES",
# Clk/Rst
i_clk=ClockSignal("sys"),
i_rst_n=~ResetSignal("sys"),
# TX
i_r_dat=sink.data,
i_r_val=sink.valid,
o_r_ena=sink.ready,
# RX
o_t_dat=source.data,
i_t_dav=source.ready,
o_t_ena=source.valid,
)

6
litex/soc/integration/soc_core.py
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@ -315,7 +315,11 @@ class SoCCore(Module):
if uart_stub: if uart_stub:
self.submodules.uart = uart.UARTStub() self.submodules.uart = uart.UARTStub()
else: else:
self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate) if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
else:
self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy)) self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True) self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True) self.add_csr("uart", allow_user_defined=True)