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Merge pull request #467 from antmicro/region_type_fix 

soc_core: Fix region type generation
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enjoy-digital 2020-04-15 07:56:48 +02:00 committed by GitHub
parent d44fe18bd9 77a05b78e8
commit a298a9e568
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litex/soc/integration/soc_core.py
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@ -244,6 +244,8 @@ class SoCCore(LiteXSoC):
for region in self.bus.regions.values(): for region in self.bus.regions.values():
region.length = region.size region.length = region.size
region.type = "cached" if region.cached else "io" region.type = "cached" if region.cached else "io"
if region.linker:
region.type += "+linker"
self.csr_regions = self.csr.regions self.csr_regions = self.csr.regions
for name, value in self.config.items(): for name, value in self.config.items():
self.add_config(name, value) self.add_config(name, value)