mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
soc/cores: remove liteeth_mini and use liteeth
This commit is contained in:
Florent Kermarrec
parent
16ba646b1b
commit
a2aa5726bf
24 changed files with 7 additions and 1808 deletions
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@ -13,9 +13,9 @@ from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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# TODO: use liteeth
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from litex.soc.cores.liteeth_mini.phy import LiteEthPHY
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from litex.soc.cores.liteeth_mini.mac import LiteEthMAC
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from liteeth.phy import LiteEthPHY
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from liteeth.core.mac import LiteEthMAC
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class _CRG(Module):
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def __init__(self, platform):
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@ -14,8 +14,8 @@ from litex.soc.cores.sdram.settings import PhySettings, IS42S16160
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from litex.soc.cores.sdram.model import SDRAMPHYModel
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from litex.soc.integration.soc_core import mem_decoder
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from litex.soc.cores.liteeth_mini.phy.model import LiteEthPHYModel
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from litex.soc.cores.liteeth_mini.mac import LiteEthMAC
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from liteeth.phy.model import LiteEthPHYModel
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from liteeth.core.mac import LiteEthMAC
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class BaseSoC(SoCSDRAM):
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def __init__(self, **kwargs):
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@ -9,10 +9,8 @@ from litex.gen.genlib.io import CRG
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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# TODO: use liteeth
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from litex.soc.cores.liteeth_mini.phy import LiteEthPHY
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from litex.soc.cores.liteeth_mini.mac import LiteEthMAC
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from liteeth.phy import LiteEthPHY
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from liteeth.core.mac import LiteEthMAC
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class BaseSoC(SoCCore):
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def __init__(self, platform, **kwargs):
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@ -1,28 +0,0 @@
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Unless otherwise noted, LiteEth is copyright (C) 2015 Florent Kermarrec.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Other authors retain ownership of their contributions. If a submission can
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reasonably be considered independently copyrightable, it's yours and we
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encourage you to claim it with appropriate copyright notices. This submission
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then falls under the "otherwise noted" category. All submissions are strongly
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encouraged to use the two-clause BSD license reproduced above.
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@ -1,58 +0,0 @@
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__ _ __ ______ __ __ ____ _
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/ / (_) /____ / __/ /_/ / / |/ (_)__ (_)
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/ /__/ / __/ -_) _// __/ _ \/ /|_/ / / _ \/ /
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/____/_/\__/\__/___/\__/_//_/_/ /_/_/_//_/_/
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Copyright 2012-2015 / EnjoyDigital / M-Labs Ltd
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A small footprint and configurable minimal Ethernet core
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powered by Migen
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[> Intro
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---------
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LiteEthMini is a subset of LiteEth (https://github.com/enjoy-digital/liteeth)
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intended to be used with a CPU and a software stack.
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[> Features
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-----------
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- Ethernet MAC with various various PHYs (GMII, MII, RGMII, Loopback)
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- SRAM storage and wishbone interface
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[> Possible improvements
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-------------------------
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- add DMA interface to MAC
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- add SGMII PHY
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr. You can also contact our partner on the public mailing list
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devel [AT] lists.m-labs.hk.
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[> License
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-----------
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LiteEthMini is released under the very permissive two-clause BSD license. Under
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the terms of this license, you are authorized to use LiteEthMini for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LiteEthMini
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- cite LiteEthMini in publications related to research it has helped
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LiteEthMini.
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[> Support and consulting
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--------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteEthMini is mainly developed and maintained by EnjoyDigital.
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If you would like to know more about LiteEthMini or if you are already a happy
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user and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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E-mail: florent [AT] enjoy-digital.fr
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@ -1,38 +0,0 @@
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from litex.gen import *
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from litex.gen.genlib.record import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.stream import *
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class Port:
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def connect(self, port):
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r = [
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Record.connect(self.source, port.sink),
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Record.connect(port.source, self.sink)
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]
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return r
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eth_mtu = 1532
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eth_min_len = 46
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eth_interpacket_gap = 12
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eth_preamble = 0xD555555555555555
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buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
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def eth_phy_description(dw):
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payload_layout = [
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("data", dw),
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("last_be", dw//8),
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("error", dw//8)
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]
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return EndpointDescription(payload_layout, packetized=True)
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def eth_mac_description(dw):
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payload_layout = mac_header.get_layout() + [
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("data", dw),
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("last_be", dw//8),
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("error", dw//8)
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]
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return EndpointDescription(payload_layout, packetized=True)
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@ -1,25 +0,0 @@
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from litex.gen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.liteeth_mini.common import *
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from litex.soc.cores.liteeth_mini.mac.core import LiteEthMACCore
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from litex.soc.cores.liteeth_mini.mac.frontend.wishbone import LiteEthMACWishboneInterface
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class LiteEthMAC(Module, AutoCSR):
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def __init__(self, phy, dw,
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interface="wishbone",
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endianness="big",
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with_preamble_crc=True):
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self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
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self.csrs = []
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if interface == "wishbone":
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self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
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self.comb += Port.connect(self.interface, self.core)
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self.ev, self.bus = self.interface.sram.ev, self.interface.bus
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self.csrs = self.interface.get_csrs() + self.core.get_csrs()
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else:
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raise NotImplementedError
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def get_csrs(self):
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return self.csrs
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@ -1,100 +0,0 @@
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from litex.gen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.liteeth_mini.common import *
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from litex.soc.cores.liteeth_mini.mac.core import gap, preamble, crc, padding, last_be
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from litex.soc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
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class LiteEthMACCore(Module, AutoCSR):
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def __init__(self, phy, dw, endianness="big",
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with_preamble_crc=True,
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with_padding=True):
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if dw < phy.dw:
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raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw))
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rx_pipeline = [phy]
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tx_pipeline = [phy]
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# Interpacket gap
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tx_gap_inserter = gap.LiteEthMACGap(phy.dw)
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rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True)
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self.submodules += ClockDomainsRenamer("eth_tx")(tx_gap_inserter)
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self.submodules += ClockDomainsRenamer("eth_rx")(rx_gap_checker)
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tx_pipeline += [tx_gap_inserter]
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rx_pipeline += [rx_gap_checker]
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# Preamble / CRC
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if with_preamble_crc:
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self._preamble_crc = CSRStatus(reset=1)
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# Preamble insert/check
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preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
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preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
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self.submodules += ClockDomainsRenamer("eth_tx")(preamble_inserter)
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self.submodules += ClockDomainsRenamer("eth_rx")(preamble_checker)
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# CRC insert/check
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crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw))
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crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw))
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self.submodules += ClockDomainsRenamer("eth_tx")(crc32_inserter)
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self.submodules += ClockDomainsRenamer("eth_rx")(crc32_checker)
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tx_pipeline += [preamble_inserter, crc32_inserter]
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rx_pipeline += [preamble_checker, crc32_checker]
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# Padding
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if with_padding:
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padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
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padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
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self.submodules += ClockDomainsRenamer("eth_tx")(padding_inserter)
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self.submodules += ClockDomainsRenamer("eth_rx")(padding_checker)
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tx_pipeline += [padding_inserter]
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rx_pipeline += [padding_checker]
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# Delimiters
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if dw != 8:
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tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw)
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rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw)
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self.submodules += ClockDomainsRenamer("eth_tx")(tx_last_be)
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self.submodules += ClockDomainsRenamer("eth_rx")(rx_last_be)
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tx_pipeline += [tx_last_be]
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rx_pipeline += [rx_last_be]
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# Converters
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if dw != phy.dw:
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reverse = endianness == "big"
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tx_converter = Converter(eth_phy_description(dw),
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eth_phy_description(phy.dw),
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reverse=reverse)
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rx_converter = Converter(eth_phy_description(phy.dw),
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eth_phy_description(dw),
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reverse=reverse)
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self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
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self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)
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tx_pipeline += [tx_converter]
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rx_pipeline += [rx_converter]
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# Cross Domain Crossing
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if isinstance(phy, LiteEthPHYMII):
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fifo_depth = 8
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else:
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fifo_depth = 64
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tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
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rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth)
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self.submodules += ClockDomainsRenamer({"write": "sys", "read": "eth_tx"})(tx_cdc)
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self.submodules += ClockDomainsRenamer({"write": "eth_rx", "read": "sys"})(rx_cdc)
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tx_pipeline += [tx_cdc]
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rx_pipeline += [rx_cdc]
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tx_pipeline_r = list(reversed(tx_pipeline))
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for s, d in zip(tx_pipeline_r, tx_pipeline_r[1:]):
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self.comb += s.source.connect(d.sink)
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for s, d in zip(rx_pipeline, rx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = tx_pipeline[-1].sink
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self.source = rx_pipeline[-1].source
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@ -1,287 +0,0 @@
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from collections import OrderedDict
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from functools import reduce
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from operator import xor
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from litex.gen import *
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from litex.gen.genlib.misc import chooser
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from litex.soc.interconnect.stream import *
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class LiteEthMACCRCEngine(Module):
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"""Cyclic Redundancy Check Engine
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Compute next CRC value from last CRC value and data input using
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an optimized asynchronous LFSR.
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Parameters
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----------
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data_width : int
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Width of the data bus.
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width : int
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Width of the CRC.
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polynom : int
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Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
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Attributes
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----------
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data : in
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Data input.
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last : in
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last CRC value.
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next :
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next CRC value.
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"""
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def __init__(self, data_width, width, polynom):
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self.data = Signal(data_width)
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self.last = Signal(width)
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self.next = Signal(width)
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# # #
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def _optimize_eq(l):
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"""
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Replace even numbers of XORs in the equation
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with an equivalent XOR
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"""
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d = OrderedDict()
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for e in l:
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if e in d:
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d[e] += 1
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else:
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d[e] = 1
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r = []
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for key, value in d.items():
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if value%2 != 0:
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r.append(key)
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return r
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# compute and optimize CRC's LFSR
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curval = [[("state", i)] for i in range(width)]
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for i in range(data_width):
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feedback = curval.pop() + [("din", i)]
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for j in range(width-1):
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if (polynom & (1<<(j+1))):
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curval[j] += feedback
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curval[j] = _optimize_eq(curval[j])
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curval.insert(0, feedback)
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# implement logic
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for i in range(width):
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xors = []
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for t, n in curval[i]:
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if t == "state":
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xors += [self.last[n]]
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elif t == "din":
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xors += [self.data[n]]
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self.comb += self.next[i].eq(reduce(xor, xors))
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@ResetInserter()
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@CEInserter()
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class LiteEthMACCRC32(Module):
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"""IEEE 802.3 CRC
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Implement an IEEE 802.3 CRC generator/checker.
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Parameters
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----------
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data_width : int
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Width of the data bus.
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Attributes
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----------
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d : in
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Data input.
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value : out
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CRC value (used for generator).
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error : out
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CRC error (used for checker).
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"""
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width = 32
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polynom = 0x04C11DB7
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init = 2**width-1
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check = 0xC704DD7B
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def __init__(self, data_width):
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self.data = Signal(data_width)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
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reg = Signal(self.width, reset=self.init)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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self.engine.data.eq(self.data),
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self.engine.last.eq(reg),
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self.value.eq(~reg[::-1]),
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self.error.eq(self.engine.next != self.check)
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]
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class LiteEthMACCRCInserter(Module):
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"""CRC Inserter
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Append a CRC at the end of each packet.
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Parameters
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----------
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description : description
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description of the dataflow.
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Attributes
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----------
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sink : in
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Packets input without CRC.
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source : out
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Packets output with CRC.
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"""
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def __init__(self, crc_class, description):
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self.sink = sink = Sink(description)
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self.source = source = Source(description)
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self.busy = Signal()
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# # #
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dw = len(sink.data)
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crc = crc_class(dw)
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fsm = FSM(reset_state="IDLE")
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self.submodules += crc, fsm
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fsm.act("IDLE",
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crc.reset.eq(1),
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("COPY"),
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)
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)
|
||||
fsm.act("COPY",
|
||||
crc.ce.eq(sink.stb & source.ack),
|
||||
crc.data.eq(sink.data),
|
||||
Record.connect(sink, source),
|
||||
source.eop.eq(0),
|
||||
If(sink.stb & sink.eop & source.ack,
|
||||
NextState("INSERT"),
|
||||
)
|
||||
)
|
||||
ratio = crc.width//dw
|
||||
if ratio > 1:
|
||||
cnt = Signal(max=ratio, reset=ratio-1)
|
||||
cnt_done = Signal()
|
||||
fsm.act("INSERT",
|
||||
source.stb.eq(1),
|
||||
chooser(crc.value, cnt, source.data, reverse=True),
|
||||
If(cnt_done,
|
||||
source.eop.eq(1),
|
||||
If(source.ack, NextState("IDLE"))
|
||||
)
|
||||
)
|
||||
self.comb += cnt_done.eq(cnt == 0)
|
||||
self.sync += \
|
||||
If(fsm.ongoing("IDLE"),
|
||||
cnt.eq(cnt.reset)
|
||||
).Elif(fsm.ongoing("INSERT") & ~cnt_done,
|
||||
cnt.eq(cnt - source.ack)
|
||||
)
|
||||
else:
|
||||
fsm.act("INSERT",
|
||||
source.stb.eq(1),
|
||||
source.eop.eq(1),
|
||||
source.data.eq(crc.value),
|
||||
If(source.ack, NextState("IDLE"))
|
||||
)
|
||||
self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
|
||||
|
||||
|
||||
class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter):
|
||||
def __init__(self, description):
|
||||
LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, description)
|
||||
|
||||
|
||||
class LiteEthMACCRCChecker(Module):
|
||||
"""CRC Checker
|
||||
|
||||
Check CRC at the end of each packet.
|
||||
|
||||
Parameters
|
||||
----------
|
||||
description : description
|
||||
description of the dataflow.
|
||||
|
||||
Attributes
|
||||
----------
|
||||
sink : in
|
||||
Packets input with CRC.
|
||||
source : out
|
||||
Packets output without CRC and "error" set to 0
|
||||
on eop when CRC OK / set to 1 when CRC KO.
|
||||
"""
|
||||
def __init__(self, crc_class, description):
|
||||
self.sink = sink = Sink(description)
|
||||
self.source = source = Source(description)
|
||||
self.busy = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
dw = len(sink.data)
|
||||
crc = crc_class(dw)
|
||||
self.submodules += crc
|
||||
ratio = crc.width//dw
|
||||
|
||||
fifo = ResetInserter()(SyncFIFO(description, ratio + 1))
|
||||
self.submodules += fifo
|
||||
|
||||
fsm = FSM(reset_state="RESET")
|
||||
self.submodules += fsm
|
||||
|
||||
fifo_in = Signal()
|
||||
fifo_out = Signal()
|
||||
fifo_full = Signal()
|
||||
|
||||
self.comb += [
|
||||
fifo_full.eq(fifo.fifo.level == ratio),
|
||||
fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
|
||||
fifo_out.eq(source.stb & source.ack),
|
||||
|
||||
Record.connect(sink, fifo.sink),
|
||||
fifo.sink.stb.eq(fifo_in),
|
||||
self.sink.ack.eq(fifo_in),
|
||||
|
||||
source.stb.eq(sink.stb & fifo_full),
|
||||
source.sop.eq(fifo.source.sop),
|
||||
source.eop.eq(sink.eop),
|
||||
fifo.source.ack.eq(fifo_out),
|
||||
source.payload.eq(fifo.source.payload),
|
||||
|
||||
source.error.eq(sink.error | crc.error),
|
||||
]
|
||||
|
||||
fsm.act("RESET",
|
||||
crc.reset.eq(1),
|
||||
fifo.reset.eq(1),
|
||||
NextState("IDLE"),
|
||||
)
|
||||
self.comb += crc.data.eq(sink.data)
|
||||
fsm.act("IDLE",
|
||||
If(sink.stb & sink.sop & sink.ack,
|
||||
crc.ce.eq(1),
|
||||
NextState("COPY")
|
||||
)
|
||||
)
|
||||
fsm.act("COPY",
|
||||
If(sink.stb & sink.ack,
|
||||
crc.ce.eq(1),
|
||||
If(sink.eop,
|
||||
NextState("RESET")
|
||||
)
|
||||
)
|
||||
)
|
||||
self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
|
||||
|
||||
|
||||
class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):
|
||||
def __init__(self, description):
|
||||
LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, description)
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
import math
|
||||
|
||||
from litex.gen import *
|
||||
from litex.gen.genlib.fsm import *
|
||||
|
||||
from litex.soc.interconnect.stream import Sink, Source
|
||||
from litex.soc.cores.liteeth_mini.common import eth_phy_description, eth_interpacket_gap
|
||||
|
||||
|
||||
class LiteEthMACGap(Module):
|
||||
def __init__(self, dw, ack_on_gap=False):
|
||||
self.sink = sink = Sink(eth_phy_description(dw))
|
||||
self.source = source = Source(eth_phy_description(dw))
|
||||
|
||||
# # #
|
||||
|
||||
gap = math.ceil(eth_interpacket_gap/(dw//8))
|
||||
counter = Signal(max=gap)
|
||||
counter_reset = Signal()
|
||||
counter_ce = Signal()
|
||||
self.sync += \
|
||||
If(counter_reset,
|
||||
counter.eq(0)
|
||||
).Elif(counter_ce,
|
||||
counter.eq(counter + 1)
|
||||
)
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="COPY")
|
||||
fsm.act("COPY",
|
||||
counter_reset.eq(1),
|
||||
Record.connect(sink, source),
|
||||
If(sink.stb & sink.eop & sink.ack,
|
||||
NextState("GAP")
|
||||
)
|
||||
)
|
||||
fsm.act("GAP",
|
||||
counter_ce.eq(1),
|
||||
sink.ack.eq(int(ack_on_gap)),
|
||||
If(counter == (gap-1),
|
||||
NextState("COPY")
|
||||
)
|
||||
)
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
from litex.gen import *
|
||||
|
||||
from litex.soc.interconnect.stream import *
|
||||
from litex.soc.cores.liteeth_mini.common import eth_phy_description
|
||||
|
||||
|
||||
class LiteEthMACTXLastBE(Module):
|
||||
def __init__(self, dw):
|
||||
self.sink = sink = Sink(eth_phy_description(dw))
|
||||
self.source = source = Source(eth_phy_description(dw))
|
||||
|
||||
# # #
|
||||
|
||||
ongoing = Signal()
|
||||
self.sync += \
|
||||
If(sink.stb & sink.ack,
|
||||
If(sink.sop,
|
||||
ongoing.eq(1)
|
||||
).Elif(sink.last_be,
|
||||
ongoing.eq(0)
|
||||
)
|
||||
)
|
||||
self.comb += [
|
||||
source.stb.eq(sink.stb & (sink.sop | ongoing)),
|
||||
source.sop.eq(sink.sop),
|
||||
source.eop.eq(sink.last_be),
|
||||
source.data.eq(sink.data),
|
||||
sink.ack.eq(source.ack)
|
||||
]
|
||||
|
||||
|
||||
class LiteEthMACRXLastBE(Module):
|
||||
def __init__(self, dw):
|
||||
self.sink = sink = Sink(eth_phy_description(dw))
|
||||
self.source = source = Source(eth_phy_description(dw))
|
||||
|
||||
# # #
|
||||
|
||||
self.comb += [
|
||||
source.stb.eq(sink.stb),
|
||||
source.sop.eq(sink.sop),
|
||||
source.eop.eq(sink.eop),
|
||||
source.data.eq(sink.data),
|
||||
source.last_be.eq(sink.eop),
|
||||
sink.ack.eq(source.ack)
|
||||
]
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
import math
|
||||
|
||||
from litex.gen import *
|
||||
|
||||
from litex.soc.interconnect.stream import *
|
||||
from litex.soc.cores.liteeth_mini.common import eth_phy_description
|
||||
|
||||
|
||||
class LiteEthMACPaddingInserter(Module):
|
||||
def __init__(self, dw, padding):
|
||||
self.sink = sink = Sink(eth_phy_description(dw))
|
||||
self.source = source = Source(eth_phy_description(dw))
|
||||
|
||||
# # #
|
||||
|
||||
padding_limit = math.ceil(padding/(dw/8))-1
|
||||
|
||||
counter = Signal(16, reset=1)
|
||||
counter_done = Signal()
|
||||
counter_reset = Signal()
|
||||
counter_ce = Signal()
|
||||
self.sync += If(counter_reset,
|
||||
counter.eq(1)
|
||||
).Elif(counter_ce,
|
||||
counter.eq(counter + 1)
|
||||
)
|
||||
self.comb += [
|
||||
counter_reset.eq(sink.stb & sink.sop & sink.ack),
|
||||
counter_ce.eq(source.stb & source.ack),
|
||||
counter_done.eq(counter >= padding_limit),
|
||||
]
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
fsm.act("IDLE",
|
||||
Record.connect(sink, source),
|
||||
If(source.stb & source.ack,
|
||||
counter_ce.eq(1),
|
||||
If(sink.eop,
|
||||
If(~counter_done,
|
||||
source.eop.eq(0),
|
||||
NextState("PADDING")
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("PADDING",
|
||||
source.stb.eq(1),
|
||||
source.eop.eq(counter_done),
|
||||
source.data.eq(0),
|
||||
If(source.ack,
|
||||
If(counter_done,
|
||||
NextState("IDLE")
|
||||
)
|
||||
)
|
||||
)
|
||||
|
||||
|
||||
class LiteEthMACPaddingChecker(Module):
|
||||
def __init__(self, dw, packet_min_length):
|
||||
self.sink = sink = Sink(eth_phy_description(dw))
|
||||
self.source = source = Source(eth_phy_description(dw))
|
||||
|
||||
# # #
|
||||
|
||||
# TODO: see if we should drop the packet when
|
||||
# payload size < minimum ethernet payload size
|
||||
self.comb += Record.connect(sink, source)
|
||||
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
from litex.gen import *
|
||||
from litex.gen.genlib.fsm import *
|
||||
from litex.gen.genlib.misc import chooser
|
||||
from litex.gen.genlib.record import Record
|
||||
|
||||
from litex.soc.interconnect.stream import *
|
||||
from litex.soc.cores.liteeth_mini.common import eth_phy_description, eth_preamble
|
||||
|
||||
|
||||
class LiteEthMACPreambleInserter(Module):
|
||||
def __init__(self, dw):
|
||||
self.sink = Sink(eth_phy_description(dw))
|
||||
self.source = Source(eth_phy_description(dw))
|
||||
|
||||
# # #
|
||||
|
||||
preamble = Signal(64, reset=eth_preamble)
|
||||
cnt_max = (64//dw)-1
|
||||
cnt = Signal(max=cnt_max+1)
|
||||
clr_cnt = Signal()
|
||||
inc_cnt = Signal()
|
||||
|
||||
self.sync += \
|
||||
If(clr_cnt,
|
||||
cnt.eq(0)
|
||||
).Elif(inc_cnt,
|
||||
cnt.eq(cnt+1)
|
||||
)
|
||||
|
||||
fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
fsm.act("IDLE",
|
||||
self.sink.ack.eq(1),
|
||||
clr_cnt.eq(1),
|
||||
If(self.sink.stb & self.sink.sop,
|
||||
self.sink.ack.eq(0),
|
||||
NextState("INSERT"),
|
||||
)
|
||||
)
|
||||
fsm.act("INSERT",
|
||||
self.source.stb.eq(1),
|
||||
self.source.sop.eq(cnt == 0),
|
||||
chooser(preamble, cnt, self.source.data),
|
||||
If(cnt == cnt_max,
|
||||
If(self.source.ack, NextState("COPY"))
|
||||
).Else(
|
||||
inc_cnt.eq(self.source.ack)
|
||||
)
|
||||
)
|
||||
|
||||
self.comb += [
|
||||
self.source.data.eq(self.sink.data),
|
||||
self.source.last_be.eq(self.sink.last_be)
|
||||
]
|
||||
fsm.act("COPY",
|
||||
Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
|
||||
self.source.sop.eq(0),
|
||||
|
||||
If(self.sink.stb & self.sink.eop & self.source.ack,
|
||||
NextState("IDLE"),
|
||||
)
|
||||
)
|
||||
|
||||
|
||||
class LiteEthMACPreambleChecker(Module):
|
||||
def __init__(self, dw):
|
||||
self.sink = Sink(eth_phy_description(dw))
|
||||
self.source = Source(eth_phy_description(dw))
|
||||
|
||||
# # #
|
||||
|
||||
preamble = Signal(64, reset=eth_preamble)
|
||||
cnt_max = (64//dw) - 1
|
||||
cnt = Signal(max=cnt_max+1)
|
||||
clr_cnt = Signal()
|
||||
inc_cnt = Signal()
|
||||
|
||||
self.sync += \
|
||||
If(clr_cnt,
|
||||
cnt.eq(0)
|
||||
).Elif(inc_cnt,
|
||||
cnt.eq(cnt+1)
|
||||
)
|
||||
|
||||
discard = Signal()
|
||||
clr_discard = Signal()
|
||||
set_discard = Signal()
|
||||
|
||||
self.sync += \
|
||||
If(clr_discard,
|
||||
discard.eq(0)
|
||||
).Elif(set_discard,
|
||||
discard.eq(1)
|
||||
)
|
||||
|
||||
sop = Signal()
|
||||
clr_sop = Signal()
|
||||
set_sop = Signal()
|
||||
self.sync += \
|
||||
If(clr_sop,
|
||||
sop.eq(0)
|
||||
).Elif(set_sop,
|
||||
sop.eq(1)
|
||||
)
|
||||
|
||||
ref = Signal(dw)
|
||||
match = Signal()
|
||||
self.comb += [
|
||||
chooser(preamble, cnt, ref),
|
||||
match.eq(self.sink.data == ref)
|
||||
]
|
||||
|
||||
fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
|
||||
fsm.act("IDLE",
|
||||
self.sink.ack.eq(1),
|
||||
clr_cnt.eq(1),
|
||||
clr_discard.eq(1),
|
||||
If(self.sink.stb & self.sink.sop,
|
||||
clr_cnt.eq(0),
|
||||
inc_cnt.eq(1),
|
||||
clr_discard.eq(0),
|
||||
set_discard.eq(~match),
|
||||
NextState("CHECK"),
|
||||
)
|
||||
)
|
||||
fsm.act("CHECK",
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
set_discard.eq(~match),
|
||||
If(cnt == cnt_max,
|
||||
If(discard | (~match),
|
||||
NextState("IDLE")
|
||||
).Else(
|
||||
set_sop.eq(1),
|
||||
NextState("COPY")
|
||||
)
|
||||
).Else(
|
||||
inc_cnt.eq(1)
|
||||
)
|
||||
)
|
||||
)
|
||||
self.comb += [
|
||||
self.source.data.eq(self.sink.data),
|
||||
self.source.last_be.eq(self.sink.last_be)
|
||||
]
|
||||
fsm.act("COPY",
|
||||
Record.connect(self.sink, self.source, leave_out=set(["data", "last_be"])),
|
||||
self.source.sop.eq(sop),
|
||||
clr_sop.eq(self.source.stb & self.source.ack),
|
||||
|
||||
If(self.source.stb & self.source.eop & self.source.ack,
|
||||
NextState("IDLE"),
|
||||
)
|
||||
)
|
||||
|
|
@ -1,252 +0,0 @@
|
|||
from litex.soc import *
|
||||
|
||||
from litex.soc.interconnect.csr import *
|
||||
from litex.soc.interconnect.csr_eventmanager import *
|
||||
from litex.soc.interconnect.stream import *
|
||||
|
||||
from litex.soc.cores.liteeth_mini.common import eth_phy_description
|
||||
|
||||
|
||||
class LiteEthMACSRAMWriter(Module, AutoCSR):
|
||||
def __init__(self, dw, depth, nslots=2):
|
||||
self.sink = sink = Sink(eth_phy_description(dw))
|
||||
self.crc_error = Signal()
|
||||
|
||||
slotbits = max(log2_int(nslots), 1)
|
||||
lengthbits = log2_int(depth*4) # length in bytes
|
||||
|
||||
self._slot = CSRStatus(slotbits)
|
||||
self._length = CSRStatus(lengthbits)
|
||||
|
||||
self.submodules.ev = EventManager()
|
||||
self.ev.available = EventSourceLevel()
|
||||
self.ev.finalize()
|
||||
|
||||
# # #
|
||||
|
||||
# packet dropped if no slot available
|
||||
sink.ack.reset = 1
|
||||
|
||||
# length computation
|
||||
increment = Signal(3)
|
||||
self.comb += \
|
||||
If(sink.last_be[3],
|
||||
increment.eq(1)
|
||||
).Elif(sink.last_be[2],
|
||||
increment.eq(2)
|
||||
).Elif(sink.last_be[1],
|
||||
increment.eq(3)
|
||||
).Else(
|
||||
increment.eq(4)
|
||||
)
|
||||
counter = Signal(lengthbits)
|
||||
counter_reset = Signal()
|
||||
counter_ce = Signal()
|
||||
self.sync += If(counter_reset,
|
||||
counter.eq(0)
|
||||
).Elif(counter_ce,
|
||||
counter.eq(counter + increment)
|
||||
)
|
||||
|
||||
# slot computation
|
||||
slot = Signal(slotbits)
|
||||
slot_ce = Signal()
|
||||
self.sync += If(slot_ce, slot.eq(slot + 1))
|
||||
|
||||
ongoing = Signal()
|
||||
|
||||
# status fifo
|
||||
fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
|
||||
self.submodules += fifo
|
||||
|
||||
# fsm
|
||||
fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
|
||||
fsm.act("IDLE",
|
||||
If(sink.stb & sink.sop,
|
||||
If(fifo.sink.ack,
|
||||
ongoing.eq(1),
|
||||
counter_ce.eq(1),
|
||||
NextState("WRITE")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("WRITE",
|
||||
counter_ce.eq(sink.stb),
|
||||
ongoing.eq(1),
|
||||
If(sink.stb & sink.eop,
|
||||
If((sink.error & sink.last_be) != 0,
|
||||
NextState("DISCARD")
|
||||
).Else(
|
||||
NextState("TERMINATE")
|
||||
)
|
||||
)
|
||||
)
|
||||
fsm.act("DISCARD",
|
||||
counter_reset.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
self.comb += [
|
||||
fifo.sink.slot.eq(slot),
|
||||
fifo.sink.length.eq(counter)
|
||||
]
|
||||
fsm.act("TERMINATE",
|
||||
counter_reset.eq(1),
|
||||
slot_ce.eq(1),
|
||||
fifo.sink.stb.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
self.comb += [
|
||||
fifo.source.ack.eq(self.ev.available.clear),
|
||||
self.ev.available.trigger.eq(fifo.source.stb),
|
||||
self._slot.status.eq(fifo.source.slot),
|
||||
self._length.status.eq(fifo.source.length),
|
||||
]
|
||||
|
||||
# memory
|
||||
mems = [None]*nslots
|
||||
ports = [None]*nslots
|
||||
for n in range(nslots):
|
||||
mems[n] = Memory(dw, depth)
|
||||
ports[n] = mems[n].get_port(write_capable=True)
|
||||
self.specials += ports[n]
|
||||
self.mems = mems
|
||||
|
||||
cases = {}
|
||||
for n, port in enumerate(ports):
|
||||
cases[n] = [
|
||||
ports[n].adr.eq(counter[2:]),
|
||||
ports[n].dat_w.eq(sink.data),
|
||||
If(sink.stb & ongoing,
|
||||
ports[n].we.eq(0xf)
|
||||
)
|
||||
]
|
||||
self.comb += Case(slot, cases)
|
||||
|
||||
|
||||
class LiteEthMACSRAMReader(Module, AutoCSR):
|
||||
def __init__(self, dw, depth, nslots=2):
|
||||
self.source = source = Source(eth_phy_description(dw))
|
||||
|
||||
slotbits = max(log2_int(nslots), 1)
|
||||
lengthbits = log2_int(depth*4) # length in bytes
|
||||
self.lengthbits = lengthbits
|
||||
|
||||
self._start = CSR()
|
||||
self._ready = CSRStatus()
|
||||
self._slot = CSRStorage(slotbits)
|
||||
self._length = CSRStorage(lengthbits)
|
||||
|
||||
self.submodules.ev = EventManager()
|
||||
self.ev.done = EventSourcePulse()
|
||||
self.ev.finalize()
|
||||
|
||||
# # #
|
||||
|
||||
# command fifo
|
||||
fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
|
||||
self.submodules += fifo
|
||||
self.comb += [
|
||||
fifo.sink.stb.eq(self._start.re),
|
||||
fifo.sink.slot.eq(self._slot.storage),
|
||||
fifo.sink.length.eq(self._length.storage),
|
||||
self._ready.status.eq(fifo.sink.ack)
|
||||
]
|
||||
|
||||
# length computation
|
||||
counter = Signal(lengthbits)
|
||||
counter_reset = Signal()
|
||||
counter_ce = Signal()
|
||||
self.sync += If(counter_reset,
|
||||
counter.eq(0)
|
||||
).Elif(counter_ce,
|
||||
counter.eq(counter + 4)
|
||||
)
|
||||
|
||||
|
||||
# fsm
|
||||
first = Signal()
|
||||
last = Signal()
|
||||
last_d = Signal()
|
||||
|
||||
fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
|
||||
fsm.act("IDLE",
|
||||
counter_reset.eq(1),
|
||||
If(fifo.source.stb,
|
||||
NextState("CHECK")
|
||||
)
|
||||
)
|
||||
fsm.act("CHECK",
|
||||
If(~last_d,
|
||||
NextState("SEND"),
|
||||
).Else(
|
||||
NextState("END"),
|
||||
)
|
||||
)
|
||||
length_lsb = fifo.source.length[0:2]
|
||||
self.comb += [
|
||||
If(last,
|
||||
If(length_lsb == 3,
|
||||
source.last_be.eq(0b0010)
|
||||
).Elif(length_lsb == 2,
|
||||
source.last_be.eq(0b0100)
|
||||
).Elif(length_lsb == 1,
|
||||
source.last_be.eq(0b1000)
|
||||
).Else(
|
||||
source.last_be.eq(0b0001)
|
||||
)
|
||||
)
|
||||
]
|
||||
fsm.act("SEND",
|
||||
source.stb.eq(1),
|
||||
source.sop.eq(first),
|
||||
source.eop.eq(last),
|
||||
If(source.ack,
|
||||
counter_ce.eq(~last),
|
||||
NextState("CHECK")
|
||||
)
|
||||
)
|
||||
fsm.act("END",
|
||||
fifo.source.ack.eq(1),
|
||||
self.ev.done.trigger.eq(1),
|
||||
NextState("IDLE")
|
||||
)
|
||||
|
||||
# first/last computation
|
||||
self.sync += [
|
||||
If(fsm.ongoing("IDLE"),
|
||||
first.eq(1)
|
||||
).Elif(source.stb & source.ack,
|
||||
first.eq(0)
|
||||
)
|
||||
]
|
||||
self.comb += last.eq((counter + 4) >= fifo.source.length)
|
||||
self.sync += last_d.eq(last)
|
||||
|
||||
# memory
|
||||
rd_slot = fifo.source.slot
|
||||
|
||||
mems = [None]*nslots
|
||||
ports = [None]*nslots
|
||||
for n in range(nslots):
|
||||
mems[n] = Memory(dw, depth)
|
||||
ports[n] = mems[n].get_port()
|
||||
self.specials += ports[n]
|
||||
self.mems = mems
|
||||
|
||||
cases = {}
|
||||
for n, port in enumerate(ports):
|
||||
self.comb += ports[n].adr.eq(counter[2:])
|
||||
cases[n] = [source.data.eq(port.dat_r)]
|
||||
self.comb += Case(rd_slot, cases)
|
||||
|
||||
|
||||
class LiteEthMACSRAM(Module, AutoCSR):
|
||||
def __init__(self, dw, depth, nrxslots, ntxslots):
|
||||
self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots)
|
||||
self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots)
|
||||
self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
|
||||
self.sink, self.source = self.writer.sink, self.reader.source
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
from litex.gen import *
|
||||
from litex.gen.fhdl.simplify import FullMemoryWE
|
||||
|
||||
from litex.soc.interconnect import wishbone
|
||||
from litex.soc.interconnect.csr import *
|
||||
from litex.soc.interconnect.stream import *
|
||||
from litex.soc.cores.liteeth_mini.common import eth_phy_description, buffer_depth
|
||||
from litex.soc.cores.liteeth_mini.mac.frontend import sram
|
||||
|
||||
|
||||
class LiteEthMACWishboneInterface(Module, AutoCSR):
|
||||
def __init__(self, dw, nrxslots=2, ntxslots=2):
|
||||
self.sink = Sink(eth_phy_description(dw))
|
||||
self.source = Source(eth_phy_description(dw))
|
||||
self.bus = wishbone.Interface()
|
||||
|
||||
# # #
|
||||
|
||||
# storage in SRAM
|
||||
sram_depth = buffer_depth//(dw//8)
|
||||
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots)
|
||||
self.comb += [
|
||||
Record.connect(self.sink, self.sram.sink),
|
||||
Record.connect(self.sram.source, self.source)
|
||||
]
|
||||
|
||||
# Wishbone interface
|
||||
wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True)
|
||||
for n in range(nrxslots)]
|
||||
# TODO: FullMemoryWE should move to Mibuild
|
||||
wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False))
|
||||
for n in range(ntxslots)]
|
||||
wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
|
||||
|
||||
wb_slaves = []
|
||||
decoderoffset = log2_int(sram_depth)
|
||||
decoderbits = log2_int(len(wb_sram_ifs))
|
||||
for n, wb_sram_if in enumerate(wb_sram_ifs):
|
||||
def slave_filter(a, v=n):
|
||||
return a[decoderoffset:decoderoffset+decoderbits] == v
|
||||
wb_slaves.append((slave_filter, wb_sram_if.bus))
|
||||
self.submodules += wb_sram_if
|
||||
wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
|
||||
self.submodules += wb_con
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
from litex.soc.cores.liteeth_mini.common import *
|
||||
|
||||
|
||||
def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
|
||||
# Autodetect PHY
|
||||
if hasattr(clock_pads, "gtx") and len(pads.tx_data) == 8:
|
||||
if hasattr(clock_pads, "tx"):
|
||||
# This is a 10/100/1G PHY
|
||||
from litex.soc.cores.liteeth_mini.phy.gmii_mii import LiteEthPHYGMIIMII
|
||||
return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
|
||||
else:
|
||||
# This is a pure 1G PHY
|
||||
from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMII
|
||||
return LiteEthPHYGMII(clock_pads, pads, **kwargs)
|
||||
elif hasattr(pads, "rx_ctl"):
|
||||
# This is a 10/100/1G RGMII PHY
|
||||
raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
|
||||
elif len(pads.tx_data) == 4:
|
||||
# This is a MII PHY
|
||||
from litex.soc.cores.liteeth_mini.phy.mii import LiteEthPHYMII
|
||||
return LiteEthPHYMII(clock_pads, pads, **kwargs)
|
||||
else:
|
||||
raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation")
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
from litex.gen import *
|
||||
from litex.gen.genlib.io import DDROutput
|
||||
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
|
||||
|
||||
from litex.soc.cores.liteeth_mini.common import *
|
||||
|
||||
|
||||
class LiteEthPHYGMIITX(Module):
|
||||
def __init__(self, pads, pads_register=True):
|
||||
self.sink = sink = Sink(eth_phy_description(8))
|
||||
|
||||
# # #
|
||||
|
||||
if hasattr(pads, "tx_er"):
|
||||
self.sync += pads.tx_er.eq(0)
|
||||
pads_eq = [
|
||||
pads.tx_en.eq(sink.stb),
|
||||
pads.tx_data.eq(sink.data)
|
||||
]
|
||||
if pads_register:
|
||||
self.sync += pads_eq
|
||||
else:
|
||||
self.comb += pads_eq
|
||||
self.comb += sink.ack.eq(1)
|
||||
|
||||
|
||||
class LiteEthPHYGMIIRX(Module):
|
||||
def __init__(self, pads):
|
||||
self.source = source = Source(eth_phy_description(8))
|
||||
|
||||
# # #
|
||||
|
||||
dv_d = Signal()
|
||||
self.sync += dv_d.eq(pads.dv)
|
||||
|
||||
sop = Signal()
|
||||
eop = Signal()
|
||||
self.comb += [
|
||||
sop.eq(pads.dv & ~dv_d),
|
||||
eop.eq(~pads.dv & dv_d)
|
||||
]
|
||||
self.sync += [
|
||||
source.stb.eq(pads.dv),
|
||||
source.sop.eq(sop),
|
||||
source.data.eq(pads.rx_data)
|
||||
]
|
||||
self.comb += source.eop.eq(eop)
|
||||
|
||||
|
||||
class LiteEthPHYGMIICRG(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
|
||||
self._reset = CSRStorage()
|
||||
|
||||
# # #
|
||||
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
|
||||
# RX : Let the synthesis tool insert the appropriate clock buffer
|
||||
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
|
||||
|
||||
# TX : GMII: Drive clock_pads.gtx, clock_pads.tx unused
|
||||
# MII: Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx
|
||||
self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
|
||||
# XXX Xilinx specific, replace BUFGMUX with a generic clock buffer?
|
||||
self.specials += Instance("BUFGMUX",
|
||||
i_I0=self.cd_eth_rx.clk,
|
||||
i_I1=clock_pads.tx,
|
||||
i_S=mii_mode,
|
||||
o_O=self.cd_eth_tx.clk)
|
||||
|
||||
if with_hw_init_reset:
|
||||
reset = Signal()
|
||||
counter = Signal(max=512)
|
||||
counter_done = Signal()
|
||||
counter_ce = Signal()
|
||||
self.sync += If(counter_ce, counter.eq(counter + 1))
|
||||
self.comb += [
|
||||
counter_done.eq(counter == 256),
|
||||
counter_ce.eq(~counter_done),
|
||||
reset.eq(~counter_done | self._reset.storage)
|
||||
]
|
||||
else:
|
||||
reset = self._reset.storage
|
||||
self.comb += pads.rst_n.eq(~reset)
|
||||
self.specials += [
|
||||
AsyncResetSynchronizer(self.cd_eth_tx, reset),
|
||||
AsyncResetSynchronizer(self.cd_eth_rx, reset),
|
||||
]
|
||||
|
||||
|
||||
class LiteEthPHYGMII(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
|
||||
self.dw = 8
|
||||
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
|
||||
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
|
||||
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
|
|
@ -1,170 +0,0 @@
|
|||
from litex.gen import *
|
||||
from litex.gen.genlib.io import DDROutput
|
||||
from litex.gen.genlib.cdc import PulseSynchronizer
|
||||
|
||||
from litex.soc.interconnect.stream import *
|
||||
from litex.soc.cores.liteeth_mini.common import *
|
||||
from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIICRG
|
||||
from litex.soc.cores.liteeth_mini.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
|
||||
from litex.soc.cores.liteeth_mini.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
|
||||
|
||||
|
||||
modes = {
|
||||
"GMII": 0,
|
||||
"MII": 1
|
||||
}
|
||||
|
||||
tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
|
||||
rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)]
|
||||
|
||||
|
||||
class LiteEthPHYGMIIMIITX(Module):
|
||||
def __init__(self, pads, mode):
|
||||
self.sink = sink = Sink(eth_phy_description(8))
|
||||
|
||||
# # #
|
||||
|
||||
gmii_tx_pads = Record(tx_pads_layout)
|
||||
gmii_tx = LiteEthPHYGMIITX(gmii_tx_pads, pads_register=False)
|
||||
self.submodules += gmii_tx
|
||||
|
||||
mii_tx_pads = Record(tx_pads_layout)
|
||||
mii_tx = LiteEthPHYMIITX(mii_tx_pads, pads_register=False)
|
||||
self.submodules += mii_tx
|
||||
|
||||
demux = Demultiplexer(eth_phy_description(8), 2)
|
||||
self.submodules += demux
|
||||
self.comb += [
|
||||
demux.sel.eq(mode == modes["MII"]),
|
||||
Record.connect(sink, demux.sink),
|
||||
Record.connect(demux.source0, gmii_tx.sink),
|
||||
Record.connect(demux.source1, mii_tx.sink),
|
||||
]
|
||||
|
||||
if hasattr(pads, "tx_er"):
|
||||
self.comb += pads.tx_er.eq(0)
|
||||
self.sync += [
|
||||
If(mode == modes["MII"],
|
||||
pads.tx_en.eq(mii_tx_pads.tx_en),
|
||||
pads.tx_data.eq(mii_tx_pads.tx_data),
|
||||
).Else(
|
||||
pads.tx_en.eq(gmii_tx_pads.tx_en),
|
||||
pads.tx_data.eq(gmii_tx_pads.tx_data),
|
||||
)
|
||||
]
|
||||
|
||||
|
||||
class LiteEthPHYGMIIMIIRX(Module):
|
||||
def __init__(self, pads, mode):
|
||||
self.source = source = Source(eth_phy_description(8))
|
||||
|
||||
# # #
|
||||
|
||||
pads_d = Record(rx_pads_layout)
|
||||
self.sync += [
|
||||
pads_d.dv.eq(pads.dv),
|
||||
pads_d.rx_data.eq(pads.rx_data)
|
||||
]
|
||||
|
||||
gmii_rx = LiteEthPHYGMIIRX(pads_d)
|
||||
self.submodules += gmii_rx
|
||||
|
||||
mii_rx = LiteEthPHYMIIRX(pads_d)
|
||||
self.submodules += mii_rx
|
||||
|
||||
mux = Multiplexer(eth_phy_description(8), 2)
|
||||
self.submodules += mux
|
||||
self.comb += [
|
||||
mux.sel.eq(mode == modes["MII"]),
|
||||
Record.connect(gmii_rx.source, mux.sink0),
|
||||
Record.connect(mii_rx.source, mux.sink1),
|
||||
Record.connect(mux.source, source)
|
||||
]
|
||||
|
||||
|
||||
class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
|
||||
def __init__(self, clk_freq):
|
||||
self.mode = Signal()
|
||||
self._mode = CSRStatus()
|
||||
|
||||
# # #
|
||||
|
||||
mode = Signal()
|
||||
update_mode = Signal()
|
||||
self.sync += \
|
||||
If(update_mode,
|
||||
self.mode.eq(mode)
|
||||
)
|
||||
self.comb += self._mode.status.eq(self.mode)
|
||||
|
||||
# Principle:
|
||||
# sys_clk >= 125MHz
|
||||
# eth_rx <= 125Mhz
|
||||
# We generate ticks every 1024 clock cycles in eth_rx domain
|
||||
# and measure ticks period in sys_clk domain.
|
||||
|
||||
# Generate a tick every 1024 clock cycles (eth_rx clock domain)
|
||||
eth_tick = Signal()
|
||||
eth_counter = Signal(10)
|
||||
self.sync.eth_rx += eth_counter.eq(eth_counter + 1)
|
||||
self.comb += eth_tick.eq(eth_counter == 0)
|
||||
|
||||
# Synchronize tick (sys clock domain)
|
||||
sys_tick = Signal()
|
||||
eth_ps = PulseSynchronizer("eth_rx", "sys")
|
||||
self.comb += [
|
||||
eth_ps.i.eq(eth_tick),
|
||||
sys_tick.eq(eth_ps.o)
|
||||
]
|
||||
self.submodules += eth_ps
|
||||
|
||||
# sys_clk domain counter
|
||||
sys_counter = Signal(24)
|
||||
sys_counter_reset = Signal()
|
||||
sys_counter_ce = Signal()
|
||||
self.sync += [
|
||||
If(sys_counter_reset,
|
||||
sys_counter.eq(0)
|
||||
).Elif(sys_counter_ce,
|
||||
sys_counter.eq(sys_counter + 1)
|
||||
)
|
||||
]
|
||||
|
||||
fsm = FSM(reset_state="IDLE")
|
||||
self.submodules += fsm
|
||||
|
||||
fsm.act("IDLE",
|
||||
sys_counter_reset.eq(1),
|
||||
If(sys_tick,
|
||||
NextState("COUNT")
|
||||
)
|
||||
)
|
||||
fsm.act("COUNT",
|
||||
sys_counter_ce.eq(1),
|
||||
If(sys_tick,
|
||||
NextState("DETECTION")
|
||||
)
|
||||
)
|
||||
fsm.act("DETECTION",
|
||||
update_mode.eq(1),
|
||||
# if freq < 125MHz-5% use MII mode
|
||||
If(sys_counter > int((clk_freq/125000000)*1024*1.05),
|
||||
mode.eq(1)
|
||||
# if freq >= 125MHz-5% use GMII mode
|
||||
).Else(
|
||||
mode.eq(0)
|
||||
),
|
||||
NextState("IDLE")
|
||||
)
|
||||
|
||||
|
||||
class LiteEthPHYGMIIMII(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads, clk_freq, with_hw_init_reset=True):
|
||||
self.dw = 8
|
||||
# Note: we can use GMII CRG since it also handles tx clock pad used for MII
|
||||
self.submodules.mode_detection = LiteEthGMIIMIIModeDetection(clk_freq)
|
||||
mode = self.mode_detection.mode
|
||||
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, mode == modes["MII"])
|
||||
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIIMIITX(pads, mode))
|
||||
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIMIIRX(pads, mode))
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
from litex.gen import *
|
||||
|
||||
from litex.soc.interconnect.csr import *
|
||||
from litex.soc.interconnect.stream import *
|
||||
from litex.soc.cores.liteeth_mini.common import *
|
||||
from litex.soc.cores.liteeth.mini.generic import *
|
||||
|
||||
|
||||
class LiteEthPHYLoopbackCRG(Module, AutoCSR):
|
||||
def __init__(self):
|
||||
self._reset = CSRStorage()
|
||||
|
||||
# # #
|
||||
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
self.comb += [
|
||||
self.cd_eth_rx.clk.eq(ClockSignal()),
|
||||
self.cd_eth_tx.clk.eq(ClockSignal())
|
||||
]
|
||||
|
||||
reset = self._reset.storage
|
||||
self.comb += [
|
||||
self.cd_eth_rx.rst.eq(reset),
|
||||
self.cd_eth_tx.rst.eq(reset)
|
||||
]
|
||||
|
||||
|
||||
class LiteEthPHYLoopback(Module, AutoCSR):
|
||||
def __init__(self):
|
||||
self.dw = 8
|
||||
self.submodules.crg = LiteEthLoopbackPHYCRG()
|
||||
self.sink = Sink(eth_phy_description(8))
|
||||
self.source = Source(eth_phy_description(8))
|
||||
self.comb += Record.connect(self.sink, self.source)
|
||||
|
|
@ -1,110 +0,0 @@
|
|||
from litex.gen import *
|
||||
|
||||
from litex.soc.interconnect.csr import *
|
||||
from litex.soc.interconnect.stream import *
|
||||
from litex.soc.cores.liteeth_mini.common import *
|
||||
|
||||
|
||||
def converter_description(dw):
|
||||
payload_layout = [("data", dw)]
|
||||
return EndpointDescription(payload_layout, packetized=True)
|
||||
|
||||
|
||||
class LiteEthPHYMIITX(Module):
|
||||
def __init__(self, pads, pads_register=True):
|
||||
self.sink = sink = Sink(eth_phy_description(8))
|
||||
|
||||
# # #
|
||||
|
||||
if hasattr(pads, "tx_er"):
|
||||
self.sync += pads.tx_er.eq(0)
|
||||
converter = Converter(converter_description(8),
|
||||
converter_description(4))
|
||||
self.submodules += converter
|
||||
self.comb += [
|
||||
converter.sink.stb.eq(sink.stb),
|
||||
converter.sink.data.eq(sink.data),
|
||||
sink.ack.eq(converter.sink.ack),
|
||||
converter.source.ack.eq(1)
|
||||
]
|
||||
pads_eq = [
|
||||
pads.tx_en.eq(converter.source.stb),
|
||||
pads.tx_data.eq(converter.source.data)
|
||||
]
|
||||
if pads_register:
|
||||
self.sync += pads_eq
|
||||
else:
|
||||
self.comb += pads_eq
|
||||
|
||||
|
||||
class LiteEthPHYMIIRX(Module):
|
||||
def __init__(self, pads):
|
||||
self.source = source = Source(eth_phy_description(8))
|
||||
|
||||
# # #
|
||||
|
||||
sop = Signal(reset=1)
|
||||
sop_set = Signal()
|
||||
sop_clr = Signal()
|
||||
self.sync += If(sop_set, sop.eq(1)).Elif(sop_clr, sop.eq(0))
|
||||
|
||||
converter = Converter(converter_description(4),
|
||||
converter_description(8))
|
||||
converter = ResetInserter()(converter)
|
||||
self.submodules += converter
|
||||
|
||||
self.sync += [
|
||||
converter.reset.eq(~pads.dv),
|
||||
converter.sink.stb.eq(1),
|
||||
converter.sink.data.eq(pads.rx_data)
|
||||
]
|
||||
self.sync += [
|
||||
sop_set.eq(~pads.dv),
|
||||
sop_clr.eq(pads.dv)
|
||||
]
|
||||
self.comb += [
|
||||
converter.sink.sop.eq(sop),
|
||||
converter.sink.eop.eq(~pads.dv)
|
||||
]
|
||||
self.comb += Record.connect(converter.source, source)
|
||||
|
||||
|
||||
class LiteEthPHYMIICRG(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads, with_hw_init_reset):
|
||||
self._reset = CSRStorage()
|
||||
|
||||
# # #
|
||||
|
||||
if hasattr(clock_pads, "phy"):
|
||||
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
|
||||
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
|
||||
self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
|
||||
|
||||
if with_hw_init_reset:
|
||||
reset = Signal()
|
||||
counter_done = Signal()
|
||||
self.submodules.counter = counter = Counter(max=512)
|
||||
self.comb += [
|
||||
counter_done.eq(counter.value == 256),
|
||||
counter.ce.eq(~counter_done),
|
||||
reset.eq(~counter_done | self._reset.storage)
|
||||
]
|
||||
else:
|
||||
reset = self._reset.storage
|
||||
self.comb += pads.rst_n.eq(~reset)
|
||||
self.specials += [
|
||||
AsyncResetSynchronizer(self.cd_eth_tx, reset),
|
||||
AsyncResetSynchronizer(self.cd_eth_rx, reset),
|
||||
]
|
||||
|
||||
|
||||
class LiteEthPHYMII(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
|
||||
self.dw = 8
|
||||
self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
|
||||
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
|
||||
self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
import os
|
||||
|
||||
from litex.soc.cores.liteeth_mini.common import *
|
||||
|
||||
|
||||
class LiteEthPHYModelCRG(Module, AutoCSR):
|
||||
def __init__(self):
|
||||
self._reset = CSRStorage()
|
||||
|
||||
# # #
|
||||
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
self.comb += [
|
||||
self.cd_eth_rx.clk.eq(ClockSignal()),
|
||||
self.cd_eth_tx.clk.eq(ClockSignal())
|
||||
]
|
||||
|
||||
reset = self._reset.storage
|
||||
self.comb += [
|
||||
self.cd_eth_rx.rst.eq(reset),
|
||||
self.cd_eth_tx.rst.eq(reset)
|
||||
]
|
||||
|
||||
|
||||
class LiteEthPHYModel(Module, AutoCSR):
|
||||
def __init__(self, pads, tap="tap0", ip_address="192.168.0.14"):
|
||||
self.dw = 8
|
||||
self.submodules.crg = LiteEthPHYModelCRG()
|
||||
self.sink = sink = Sink(eth_phy_description(8))
|
||||
self.source = source = Source(eth_phy_description(8))
|
||||
self.tap = tap
|
||||
self.ip_address = ip_address
|
||||
|
||||
self.comb += [
|
||||
pads.source_stb.eq(self.sink.stb),
|
||||
pads.source_data.eq(self.sink.data),
|
||||
self.sink.ack.eq(1)
|
||||
]
|
||||
|
||||
self.sync += [
|
||||
self.source.stb.eq(pads.sink_stb),
|
||||
self.source.sop.eq(pads.sink_stb & ~self.source.stb),
|
||||
self.source.data.eq(pads.sink_data),
|
||||
]
|
||||
self.comb += [
|
||||
self.source.eop.eq(~pads.sink_stb & self.source.stb),
|
||||
]
|
||||
|
||||
# TODO avoid use of os.system
|
||||
os.system("openvpn --mktun --dev {}".format(self.tap))
|
||||
os.system("ifconfig {} {} up".format(self.tap, self.ip_address))
|
||||
os.system("mknod /dev/net/{} c 10 200".format(self.tap))
|
||||
|
||||
def do_exit(self, *args, **kwargs):
|
||||
# TODO avoid use of os.system
|
||||
os.system("rm -f /dev/net/{}".format(self.tap))
|
||||
os.system("openvpn --rmtun --dev {}".format(self.tap))
|
||||
|
|
@ -1,161 +0,0 @@
|
|||
# RGMII PHY for Spartan-6
|
||||
|
||||
from litex.gen import *
|
||||
from litex.gen.genlib.io import DDROutput
|
||||
from litex.gen.genlib.misc import WaitTimer
|
||||
from litex.gen.genlib.fsm import FSM, NextState
|
||||
|
||||
from litex.soc.interconnect.stream import *
|
||||
from litex.soc.interconnect.csr import *
|
||||
from litex.soc.cores.liteeth_mini.common import *
|
||||
|
||||
|
||||
class LiteEthPHYRGMIITX(Module):
|
||||
def __init__(self, pads, pads_register=True):
|
||||
self.sink = sink = Sink(eth_phy_description(8))
|
||||
|
||||
# # #
|
||||
|
||||
self.specials += Instance("ODDR2",
|
||||
p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
|
||||
i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"),
|
||||
i_CE=1, i_S=0, i_R=0,
|
||||
i_D0=sink.stb, i_D1=sink.stb, o_Q=pads.tx_ctl,
|
||||
)
|
||||
for i in range(4):
|
||||
self.specials += Instance("ODDR2",
|
||||
p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
|
||||
i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"),
|
||||
i_CE=1, i_S=0, i_R=0,
|
||||
i_D0=sink.data[i], i_D1=sink.data[4+i], o_Q=pads.tx_data[i],
|
||||
)
|
||||
self.comb += sink.ack.eq(1)
|
||||
|
||||
|
||||
class LiteEthPHYRGMIIRX(Module):
|
||||
def __init__(self, pads):
|
||||
self.source = source = Source(eth_phy_description(8))
|
||||
|
||||
# # #
|
||||
|
||||
rx_ctl = Signal()
|
||||
rx_data = Signal(8)
|
||||
|
||||
self.specials += Instance("IDDR2",
|
||||
p_DDR_ALIGNMENT="C0", p_INIT_Q0=0, p_INIT_Q1=0, p_SRTYPE="ASYNC",
|
||||
i_C0=ClockSignal("eth_rx"), i_C1=~ClockSignal("eth_rx"),
|
||||
i_CE=1, i_S=0, i_R=0,
|
||||
i_D=pads.rx_ctl, o_Q1=rx_ctl,
|
||||
)
|
||||
for i in range(4):
|
||||
self.specials += Instance("IDDR2",
|
||||
p_DDR_ALIGNMENT="C0", p_INIT_Q0=0, p_INIT_Q1=0, p_SRTYPE="ASYNC",
|
||||
i_C0=ClockSignal("eth_rx"), i_C1=~ClockSignal("eth_rx"),
|
||||
i_CE=1, i_S=0, i_R=0,
|
||||
i_D=pads.rx_data[i], o_Q0=rx_data[4+i], o_Q1=rx_data[i],
|
||||
)
|
||||
|
||||
|
||||
rx_ctl_d = Signal()
|
||||
self.sync += rx_ctl_d.eq(rx_ctl)
|
||||
|
||||
sop = Signal()
|
||||
eop = Signal()
|
||||
self.comb += [
|
||||
sop.eq(rx_ctl & ~rx_ctl_d),
|
||||
eop.eq(~rx_ctl & rx_ctl_d)
|
||||
]
|
||||
self.sync += [
|
||||
source.stb.eq(rx_ctl),
|
||||
source.sop.eq(sop),
|
||||
source.data.eq(rx_data)
|
||||
]
|
||||
self.comb += source.eop.eq(eop)
|
||||
|
||||
|
||||
class LiteEthPHYRGMIICRG(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads, with_hw_init_reset):
|
||||
self._reset = CSRStorage()
|
||||
|
||||
# # #
|
||||
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
|
||||
|
||||
# RX
|
||||
dcm_reset = Signal()
|
||||
dcm_locked = Signal()
|
||||
|
||||
timer = WaitTimer(1024)
|
||||
fsm = FSM(reset_state="DCM_RESET")
|
||||
self.submodules += timer, fsm
|
||||
|
||||
fsm.act("DCM_RESET",
|
||||
dcm_reset.eq(1),
|
||||
timer.wait.eq(1),
|
||||
If(timer.done,
|
||||
timer.wait.eq(0),
|
||||
NextState("DCM_WAIT")
|
||||
)
|
||||
)
|
||||
fsm.act("DCM_WAIT",
|
||||
timer.wait.eq(1),
|
||||
If(timer.done,
|
||||
NextState("DCM_CHECK_LOCK")
|
||||
)
|
||||
)
|
||||
fsm.act("DCM_CHECK_LOCK",
|
||||
If(~dcm_locked,
|
||||
NextState("DCM_RESET")
|
||||
)
|
||||
)
|
||||
|
||||
clk90_rx = Signal()
|
||||
clk0_rx = Signal()
|
||||
clk0_rx_bufg = Signal()
|
||||
self.specials += Instance("DCM",
|
||||
i_CLKIN=clock_pads.rx,
|
||||
i_CLKFB=clk0_rx_bufg,
|
||||
o_CLK0=clk0_rx,
|
||||
o_CLK90=clk90_rx,
|
||||
o_LOCKED=dcm_locked,
|
||||
i_PSEN=0,
|
||||
i_PSCLK=0,
|
||||
i_PSINCDEC=0,
|
||||
i_RST=dcm_reset
|
||||
)
|
||||
|
||||
self.specials += Instance("BUFG", i_I=clk0_rx, o_O=clk0_rx_bufg)
|
||||
self.specials += Instance("BUFG", i_I=clk90_rx, o_O=self.cd_eth_rx.clk)
|
||||
|
||||
# TX
|
||||
self.specials += DDROutput(1, 0, clock_pads.tx, ClockSignal("eth_tx"))
|
||||
self.specials += Instance("BUFG", i_I=self.cd_eth_rx.clk, o_O=self.cd_eth_tx.clk)
|
||||
|
||||
# Reset
|
||||
if with_hw_init_reset:
|
||||
reset = Signal()
|
||||
counter_done = Signal()
|
||||
self.submodules.counter = counter = Counter(max=512)
|
||||
self.comb += [
|
||||
counter_done.eq(counter.value == 256),
|
||||
counter.ce.eq(~counter_done),
|
||||
reset.eq(~counter_done | self._reset.storage)
|
||||
]
|
||||
else:
|
||||
reset = self._reset.storage
|
||||
self.comb += pads.rst_n.eq(~reset)
|
||||
self.specials += [
|
||||
AsyncResetSynchronizer(self.cd_eth_tx, reset),
|
||||
AsyncResetSynchronizer(self.cd_eth_rx, reset),
|
||||
]
|
||||
|
||||
|
||||
class LiteEthPHYRGMII(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
|
||||
self.dw = 8
|
||||
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
|
||||
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
|
||||
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
|
||||
self.sink, self.source = self.tx.sink, self.rx.source
|
||||
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Reference in a new issue