soc: change default CSR bus data-width to 32.

A CSR bus data-width of 32 has been validated on very various design and is
now recommended. It provides better performance without impacting resource
usage (even on iCE40).
This commit is contained in:
Florent Kermarrec 2020-10-07 16:35:08 +02:00
parent 4f30a5b8e5
commit a2b71fde4a
3 changed files with 4 additions and 3 deletions

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@ -27,6 +27,7 @@
--------------------------
- BIOS: commands have been renamed/reorganized.
- LiteDRAM: rdcmdphase/wrcmdphase no longer exposed.
- CSR: change default csr_data_width from 8 to 32.
[> 2020.08, planned for July 2020
---------------------------------

View File

@ -63,7 +63,7 @@ class DocumentedCSR:
f.description = self.trim(f.description)
class DocumentedCSRRegion:
def __init__(self, name, region, module=None, submodules=[], csr_data_width=8):
def __init__(self, name, region, module=None, submodules=[], csr_data_width=32):
self.name = name
self.origin = region.origin
self.busword = region.busword

View File

@ -80,7 +80,7 @@ class SoCCore(LiteXSoC):
integrated_main_ram_size = 0,
integrated_main_ram_init = [],
# CSR parameters
csr_data_width = 8,
csr_data_width = 32,
csr_address_width = 14,
csr_paging = 0x800,
csr_ordering = "big",
@ -282,7 +282,7 @@ def soc_core_args(parser):
help="size/enable the integrated main RAM")
# CSR parameters
parser.add_argument("--csr-data-width", default=None, type=auto_int,
help="CSR bus data-width (8 or 32, default=8)")
help="CSR bus data-width (8 or 32, default=32)")
parser.add_argument("--csr-address-width", default=14, type=auto_int,
help="CSR bus address-width")
parser.add_argument("--csr-paging", default=0x800, type=auto_int,