soc: change default CSR bus data-width to 32.
A CSR bus data-width of 32 has been validated on very various design and is now recommended. It provides better performance without impacting resource usage (even on iCE40).
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@ -27,6 +27,7 @@
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--------------------------
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- BIOS: commands have been renamed/reorganized.
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- LiteDRAM: rdcmdphase/wrcmdphase no longer exposed.
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- CSR: change default csr_data_width from 8 to 32.
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[> 2020.08, planned for July 2020
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---------------------------------
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@ -63,7 +63,7 @@ class DocumentedCSR:
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f.description = self.trim(f.description)
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class DocumentedCSRRegion:
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def __init__(self, name, region, module=None, submodules=[], csr_data_width=8):
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def __init__(self, name, region, module=None, submodules=[], csr_data_width=32):
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self.name = name
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self.origin = region.origin
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self.busword = region.busword
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@ -80,7 +80,7 @@ class SoCCore(LiteXSoC):
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integrated_main_ram_size = 0,
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integrated_main_ram_init = [],
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# CSR parameters
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csr_data_width = 8,
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csr_data_width = 32,
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csr_address_width = 14,
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csr_paging = 0x800,
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csr_ordering = "big",
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@ -282,7 +282,7 @@ def soc_core_args(parser):
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help="size/enable the integrated main RAM")
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# CSR parameters
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parser.add_argument("--csr-data-width", default=None, type=auto_int,
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help="CSR bus data-width (8 or 32, default=8)")
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help="CSR bus data-width (8 or 32, default=32)")
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parser.add_argument("--csr-address-width", default=14, type=auto_int,
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help="CSR bus address-width")
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parser.add_argument("--csr-paging", default=0x800, type=auto_int,
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