Merge pull request #402 from antmicro/litex-gen-fix-uart-pins

tools: litex_gen: fix missing UART pins
2020-02-25 15:53:13 +01:00 · 2020-02-25 15:53:13 +01:00 · a2d6986910
parent e2aebb427e 75b000a32f
commit a2d6986910
1 changed files with 9 additions and 0 deletions
--- a/litex/tools/litex_gen.py
+++ b/litex/tools/litex_gen.py
@ -49,6 +49,15 @@ class LiteXCore(SoCMini):

        platform = Platform(_io)

+        # UART
+        if kwargs["with_uart"]:
+            platform.add_extension([
+                ("serial", 0,
+                    Subsignal("tx",  Pins(1)),
+                    Subsignal("rx", Pins(1)),
+                )
+            ])
+
        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))