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Merge pull request #402 from antmicro/litex-gen-fix-uart-pins 

tools: litex_gen: fix missing UART pins
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enjoy-digital 2020-02-25 15:53:13 +01:00 committed by GitHub
parent e2aebb427e 75b000a32f
commit a2d6986910
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litex/tools/litex_gen.py
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@ -49,6 +49,15 @@ class LiteXCore(SoCMini):
platform = Platform(_io) platform = Platform(_io)
# UART
if kwargs["with_uart"]:
platform.add_extension([
("serial", 0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
)
])
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst")) self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))